185f199b7SChia-Wei Wang /* 285f199b7SChia-Wei Wang * Copyright (c) 2023, Aspeed Technology Inc. 385f199b7SChia-Wei Wang * 485f199b7SChia-Wei Wang * SPDX-License-Identifier: BSD-3-Clause 585f199b7SChia-Wei Wang */ 685f199b7SChia-Wei Wang 785f199b7SChia-Wei Wang #ifndef PLATFORM_REG_H 885f199b7SChia-Wei Wang #define PLATFORM_REG_H 985f199b7SChia-Wei Wang 1085f199b7SChia-Wei Wang /* GIC */ 1185f199b7SChia-Wei Wang #define GICD_BASE U(0x12200000) 1285f199b7SChia-Wei Wang #define GICD_SIZE U(0x10000) 1385f199b7SChia-Wei Wang #define GICR_BASE U(0x12280000) 1485f199b7SChia-Wei Wang #define GICR_SIZE U(0x100000) 1585f199b7SChia-Wei Wang 1685f199b7SChia-Wei Wang /* UART */ 1785f199b7SChia-Wei Wang #define UART_BASE U(0x14c33000) 1885f199b7SChia-Wei Wang #define UART12_BASE (UART_BASE + 0xb00) 1985f199b7SChia-Wei Wang 2085f199b7SChia-Wei Wang /* CPU-die SCU */ 2185f199b7SChia-Wei Wang #define SCU_CPU_BASE U(0x12c02000) 22*564e073cSChia-Wei Wang #define SCU_CPU_SMP_EP0 (SCU_CPU_BASE + 0x780) 2385f199b7SChia-Wei Wang #define SCU_CPU_SMP_EP1 (SCU_CPU_BASE + 0x788) 2485f199b7SChia-Wei Wang #define SCU_CPU_SMP_EP2 (SCU_CPU_BASE + 0x790) 2585f199b7SChia-Wei Wang #define SCU_CPU_SMP_EP3 (SCU_CPU_BASE + 0x798) 2685f199b7SChia-Wei Wang 2785f199b7SChia-Wei Wang #endif /* PLATFORM_REG_H */ 28