1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <board_css_def.h> 32 #include <mmio.h> 33 #include <nic_400.h> 34 #include <platform_def.h> 35 #include <soc_css_def.h> 36 37 void soc_css_init_nic400(void) 38 { 39 /* 40 * NIC-400 Access Control Initialization 41 * 42 * Define access privileges by setting each corresponding bit to: 43 * 0 = Secure access only 44 * 1 = Non-secure access allowed 45 */ 46 47 /* 48 * Allow non-secure access to some SOC regions, excluding UART1, which 49 * remains secure. 50 * Note: This is the NIC-400 device on the SOC 51 */ 52 mmio_write_32(SOC_CSS_NIC400_BASE + 53 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_USB_EHCI), ~0); 54 mmio_write_32(SOC_CSS_NIC400_BASE + 55 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_TLX_MASTER), ~0); 56 mmio_write_32(SOC_CSS_NIC400_BASE + 57 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_USB_OHCI), ~0); 58 mmio_write_32(SOC_CSS_NIC400_BASE + 59 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_PL354_SMC), ~0); 60 mmio_write_32(SOC_CSS_NIC400_BASE + 61 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_APB4_BRIDGE), ~0); 62 mmio_write_32(SOC_CSS_NIC400_BASE + 63 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_BOOTSEC_BRIDGE), 64 ~SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1); 65 66 } 67 68 69 #define PCIE_SECURE_REG 0x3000 70 /* Mask uses REG and MEM access bits */ 71 #define PCIE_SEC_ACCESS_MASK ((1 << 0) | (1 << 1)) 72 73 void soc_css_init_pcie(void) 74 { 75 #if !PLAT_juno 76 /* 77 * Do not initialize PCIe in emulator environment. 78 * Platform ID register not supported on Juno 79 */ 80 if (BOARD_CSS_GET_PLAT_TYPE(BOARD_CSS_PLAT_ID_REG_ADDR) == 81 BOARD_CSS_PLAT_TYPE_EMULATOR) 82 return; 83 #endif /* PLAT_juno */ 84 85 /* 86 * PCIE Root Complex Security settings to enable non-secure 87 * access to config registers. 88 */ 89 mmio_write_32(SOC_CSS_PCIE_CONTROL_BASE + PCIE_SECURE_REG, 90 PCIE_SEC_ACCESS_MASK); 91 } 92