1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <platform_def.h> 8 9 #include <drivers/arm/nic_400.h> 10 #include <lib/mmio.h> 11 #include <plat/arm/soc/common/soc_css.h> 12 13 void soc_css_init_nic400(void) 14 { 15 /* 16 * NIC-400 Access Control Initialization 17 * 18 * Define access privileges by setting each corresponding bit to: 19 * 0 = Secure access only 20 * 1 = Non-secure access allowed 21 */ 22 23 /* 24 * Allow non-secure access to some SOC regions, excluding UART1, which 25 * remains secure (unless CSS_NON_SECURE_UART is set). 26 * Note: This is the NIC-400 device on the SOC 27 */ 28 mmio_write_32(SOC_CSS_NIC400_BASE + 29 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_USB_EHCI), ~0); 30 mmio_write_32(SOC_CSS_NIC400_BASE + 31 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_TLX_MASTER), ~0); 32 mmio_write_32(SOC_CSS_NIC400_BASE + 33 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_USB_OHCI), ~0); 34 mmio_write_32(SOC_CSS_NIC400_BASE + 35 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_PL354_SMC), ~0); 36 mmio_write_32(SOC_CSS_NIC400_BASE + 37 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_APB4_BRIDGE), ~0); 38 #if CSS_NON_SECURE_UART 39 /* Configure UART for non-secure access */ 40 mmio_write_32(SOC_CSS_NIC400_BASE + 41 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_BOOTSEC_BRIDGE), ~0); 42 #else 43 mmio_write_32(SOC_CSS_NIC400_BASE + 44 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_BOOTSEC_BRIDGE), 45 ~SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1); 46 #endif /* CSS_NON_SECURE_UART */ 47 48 } 49 50 51 #define PCIE_SECURE_REG 0x3000 52 /* Mask uses REG and MEM access bits */ 53 #define PCIE_SEC_ACCESS_MASK ((1 << 0) | (1 << 1)) 54 55 void soc_css_init_pcie(void) 56 { 57 #if !PLAT_juno 58 /* 59 * Do not initialize PCIe in emulator environment. 60 * Platform ID register not supported on Juno 61 */ 62 if (BOARD_CSS_GET_PLAT_TYPE(BOARD_CSS_PLAT_ID_REG_ADDR) == 63 BOARD_CSS_PLAT_TYPE_EMULATOR) 64 return; 65 #endif /* PLAT_juno */ 66 67 /* 68 * PCIE Root Complex Security settings to enable non-secure 69 * access to config registers. 70 */ 71 mmio_write_32(SOC_CSS_PCIE_CONTROL_BASE + PCIE_SECURE_REG, 72 PCIE_SEC_ACCESS_MASK); 73 } 74