1b4315306SDan Handley /* 2b4315306SDan Handley * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3b4315306SDan Handley * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5b4315306SDan Handley */ 6b4315306SDan Handley 7b4315306SDan Handley #include <board_css_def.h> 8b4315306SDan Handley #include <mmio.h> 9883852caSVikram Kanigiri #include <nic_400.h> 10b4315306SDan Handley #include <platform_def.h> 11b4315306SDan Handley #include <soc_css_def.h> 12b4315306SDan Handley 13b4315306SDan Handley void soc_css_init_nic400(void) 14b4315306SDan Handley { 15b4315306SDan Handley /* 16b4315306SDan Handley * NIC-400 Access Control Initialization 17b4315306SDan Handley * 18b4315306SDan Handley * Define access privileges by setting each corresponding bit to: 19b4315306SDan Handley * 0 = Secure access only 20b4315306SDan Handley * 1 = Non-secure access allowed 21b4315306SDan Handley */ 22b4315306SDan Handley 23b4315306SDan Handley /* 24b4315306SDan Handley * Allow non-secure access to some SOC regions, excluding UART1, which 25b4315306SDan Handley * remains secure. 26b4315306SDan Handley * Note: This is the NIC-400 device on the SOC 27b4315306SDan Handley */ 28b4315306SDan Handley mmio_write_32(SOC_CSS_NIC400_BASE + 29b4315306SDan Handley NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_USB_EHCI), ~0); 30b4315306SDan Handley mmio_write_32(SOC_CSS_NIC400_BASE + 31b4315306SDan Handley NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_TLX_MASTER), ~0); 32b4315306SDan Handley mmio_write_32(SOC_CSS_NIC400_BASE + 33b4315306SDan Handley NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_USB_OHCI), ~0); 34b4315306SDan Handley mmio_write_32(SOC_CSS_NIC400_BASE + 35b4315306SDan Handley NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_PL354_SMC), ~0); 36b4315306SDan Handley mmio_write_32(SOC_CSS_NIC400_BASE + 37b4315306SDan Handley NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_APB4_BRIDGE), ~0); 38b4315306SDan Handley mmio_write_32(SOC_CSS_NIC400_BASE + 39b4315306SDan Handley NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_BOOTSEC_BRIDGE), 40b4315306SDan Handley ~SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1); 41b4315306SDan Handley 42b4315306SDan Handley } 43b4315306SDan Handley 44b4315306SDan Handley 45b4315306SDan Handley #define PCIE_SECURE_REG 0x3000 46b4315306SDan Handley /* Mask uses REG and MEM access bits */ 47b4315306SDan Handley #define PCIE_SEC_ACCESS_MASK ((1 << 0) | (1 << 1)) 48b4315306SDan Handley 49b4315306SDan Handley void soc_css_init_pcie(void) 50b4315306SDan Handley { 51b4315306SDan Handley #if !PLAT_juno 52b4315306SDan Handley /* 53b4315306SDan Handley * Do not initialize PCIe in emulator environment. 54b4315306SDan Handley * Platform ID register not supported on Juno 55b4315306SDan Handley */ 56b4315306SDan Handley if (BOARD_CSS_GET_PLAT_TYPE(BOARD_CSS_PLAT_ID_REG_ADDR) == 57b4315306SDan Handley BOARD_CSS_PLAT_TYPE_EMULATOR) 58b4315306SDan Handley return; 59b4315306SDan Handley #endif /* PLAT_juno */ 60b4315306SDan Handley 61b4315306SDan Handley /* 62b4315306SDan Handley * PCIE Root Complex Security settings to enable non-secure 63b4315306SDan Handley * access to config registers. 64b4315306SDan Handley */ 65b4315306SDan Handley mmio_write_32(SOC_CSS_PCIE_CONTROL_BASE + PCIE_SECURE_REG, 66b4315306SDan Handley PCIE_SEC_ACCESS_MASK); 67b4315306SDan Handley } 68