1*38dce70fSSoby Mathew /* 2*38dce70fSSoby Mathew * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3*38dce70fSSoby Mathew * 4*38dce70fSSoby Mathew * Redistribution and use in source and binary forms, with or without 5*38dce70fSSoby Mathew * modification, are permitted provided that the following conditions are met: 6*38dce70fSSoby Mathew * 7*38dce70fSSoby Mathew * Redistributions of source code must retain the above copyright notice, this 8*38dce70fSSoby Mathew * list of conditions and the following disclaimer. 9*38dce70fSSoby Mathew * 10*38dce70fSSoby Mathew * Redistributions in binary form must reproduce the above copyright notice, 11*38dce70fSSoby Mathew * this list of conditions and the following disclaimer in the documentation 12*38dce70fSSoby Mathew * and/or other materials provided with the distribution. 13*38dce70fSSoby Mathew * 14*38dce70fSSoby Mathew * Neither the name of ARM nor the names of its contributors may be used 15*38dce70fSSoby Mathew * to endorse or promote products derived from this software without specific 16*38dce70fSSoby Mathew * prior written permission. 17*38dce70fSSoby Mathew * 18*38dce70fSSoby Mathew * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*38dce70fSSoby Mathew * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*38dce70fSSoby Mathew * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*38dce70fSSoby Mathew * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*38dce70fSSoby Mathew * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*38dce70fSSoby Mathew * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*38dce70fSSoby Mathew * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*38dce70fSSoby Mathew * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*38dce70fSSoby Mathew * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*38dce70fSSoby Mathew * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*38dce70fSSoby Mathew * POSSIBILITY OF SUCH DAMAGE. 29*38dce70fSSoby Mathew */ 30*38dce70fSSoby Mathew 31*38dce70fSSoby Mathew #include <plat_arm.h> 32*38dce70fSSoby Mathew 33*38dce70fSSoby Mathew /* 34*38dce70fSSoby Mathew * On ARM platforms, by default the cluster power level is treated as the 35*38dce70fSSoby Mathew * highest. The first entry in the power domain descriptor specifies the 36*38dce70fSSoby Mathew * number of cluster power domains i.e. 2. 37*38dce70fSSoby Mathew */ 38*38dce70fSSoby Mathew #define CSS_PWR_DOMAINS_AT_MAX_PWR_LVL ARM_CLUSTER_COUNT 39*38dce70fSSoby Mathew 40*38dce70fSSoby Mathew /* 41*38dce70fSSoby Mathew * The CSS power domain tree descriptor. The cluster power domains are 42*38dce70fSSoby Mathew * arranged so that when the PSCI generic code creates the power domain tree, 43*38dce70fSSoby Mathew * the indices of the CPU power domain nodes it allocates match the linear 44*38dce70fSSoby Mathew * indices returned by plat_core_pos_by_mpidr() i.e. 45*38dce70fSSoby Mathew * CLUSTER1 CPUs are allocated indices from 0 to 3 and the higher indices for 46*38dce70fSSoby Mathew * CLUSTER0 CPUs. 47*38dce70fSSoby Mathew */ 48*38dce70fSSoby Mathew const unsigned char arm_power_domain_tree_desc[] = { 49*38dce70fSSoby Mathew /* No of root nodes */ 50*38dce70fSSoby Mathew CSS_PWR_DOMAINS_AT_MAX_PWR_LVL, 51*38dce70fSSoby Mathew /* No of children for the first node */ 52*38dce70fSSoby Mathew PLAT_ARM_CLUSTER1_CORE_COUNT, 53*38dce70fSSoby Mathew /* No of children for the second node */ 54*38dce70fSSoby Mathew PLAT_ARM_CLUSTER0_CORE_COUNT 55*38dce70fSSoby Mathew }; 56*38dce70fSSoby Mathew 57*38dce70fSSoby Mathew 58*38dce70fSSoby Mathew /****************************************************************************** 59*38dce70fSSoby Mathew * This function implements a part of the critical interface between the psci 60*38dce70fSSoby Mathew * generic layer and the platform that allows the former to query the platform 61*38dce70fSSoby Mathew * to convert an MPIDR to a unique linear index. An error code (-1) is 62*38dce70fSSoby Mathew * returned in case the MPIDR is invalid. 63*38dce70fSSoby Mathew *****************************************************************************/ 64*38dce70fSSoby Mathew int plat_core_pos_by_mpidr(u_register_t mpidr) 65*38dce70fSSoby Mathew { 66*38dce70fSSoby Mathew if (arm_check_mpidr(mpidr) == 0) 67*38dce70fSSoby Mathew return plat_arm_calc_core_pos(mpidr); 68*38dce70fSSoby Mathew 69*38dce70fSSoby Mathew return -1; 70*38dce70fSSoby Mathew } 71