1/* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30#include <arch.h> 31#include <asm_macros.S> 32#include <cpu_macros.S> 33#include <css_def.h> 34 35 .weak plat_secondary_cold_boot_setup 36 .weak plat_get_my_entrypoint 37 .globl css_calc_core_pos_swap_cluster 38 .weak plat_is_my_cpu_primary 39 40 /* --------------------------------------------------------------------- 41 * void plat_secondary_cold_boot_setup(void); 42 * 43 * In the normal boot flow, cold-booting secondary CPUs is not yet 44 * implemented and they panic. 45 * 46 * When booting an EL3 payload, secondary CPUs are placed in a holding 47 * pen, waiting for their mailbox to be populated. Note that all CPUs 48 * share the same mailbox ; therefore, populating it will release all 49 * CPUs from their holding pen. If finer-grained control is needed then 50 * this should be handled in the code that secondary CPUs jump to. 51 * --------------------------------------------------------------------- 52 */ 53func plat_secondary_cold_boot_setup 54#ifndef EL3_PAYLOAD_BASE 55 /* TODO: Implement secondary CPU cold boot setup on CSS platforms */ 56cb_panic: 57 b cb_panic 58#else 59 mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE 60 61 /* Wait until the mailbox gets populated */ 62poll_mailbox: 63 ldr x1, [x0] 64 cbz x1, 1f 65 br x1 661: 67 wfe 68 b poll_mailbox 69#endif /* EL3_PAYLOAD_BASE */ 70endfunc plat_secondary_cold_boot_setup 71 72 /* --------------------------------------------------------------------- 73 * uintptr_t plat_get_my_entrypoint (void); 74 * 75 * Main job of this routine is to distinguish between a cold and a warm 76 * boot. On CSS platforms, this distinction is based on the contents of 77 * the Trusted Mailbox. It is initialised to zero by the SCP before the 78 * AP cores are released from reset. Therefore, a zero mailbox means 79 * it's a cold reset. 80 * 81 * This functions returns the contents of the mailbox, i.e.: 82 * - 0 for a cold boot; 83 * - the warm boot entrypoint for a warm boot. 84 * --------------------------------------------------------------------- 85 */ 86func plat_get_my_entrypoint 87 mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE 88 ldr x0, [x0] 89 ret 90endfunc plat_get_my_entrypoint 91 92 /* ----------------------------------------------------------- 93 * unsigned int css_calc_core_pos_swap_cluster(u_register_t mpidr) 94 * Utility function to calculate the core position by 95 * swapping the cluster order. This is necessary in order to 96 * match the format of the boot information passed by the SCP 97 * and read in plat_is_my_cpu_primary below. 98 * ----------------------------------------------------------- 99 */ 100func css_calc_core_pos_swap_cluster 101 and x1, x0, #MPIDR_CPU_MASK 102 and x0, x0, #MPIDR_CLUSTER_MASK 103 eor x0, x0, #(1 << MPIDR_AFFINITY_BITS) // swap cluster order 104 add x0, x1, x0, LSR #6 105 ret 106endfunc css_calc_core_pos_swap_cluster 107 108 /* ----------------------------------------------------- 109 * unsigned int plat_is_my_cpu_primary (void); 110 * 111 * Find out whether the current cpu is the primary 112 * cpu (applicable ony after a cold boot) 113 * ----------------------------------------------------- 114 */ 115func plat_is_my_cpu_primary 116 mov x9, x30 117 bl plat_my_core_pos 118 ldr x1, =SCP_BOOT_CFG_ADDR 119 ldr x1, [x1] 120 ubfx x1, x1, #PLAT_CSS_PRIMARY_CPU_SHIFT, \ 121 #PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 122 cmp x0, x1 123 cset w0, eq 124 ret x9 125endfunc plat_is_my_cpu_primary 126