1b4315306SDan Handley/* 28e083ecdSVikram Kanigiri * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3b4315306SDan Handley * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5b4315306SDan Handley */ 6b4315306SDan Handley#include <arch.h> 7b4315306SDan Handley#include <asm_macros.S> 8b4315306SDan Handley#include <cpu_macros.S> 9b4315306SDan Handley#include <css_def.h> 10b4315306SDan Handley 11b4315306SDan Handley .weak plat_secondary_cold_boot_setup 1238dce70fSSoby Mathew .weak plat_get_my_entrypoint 13371d4399SDavid Wang .globl css_calc_core_pos_swap_cluster 1438dce70fSSoby Mathew .weak plat_is_my_cpu_primary 15b4315306SDan Handley 162bc42067SSandrine Bailleux /* --------------------------------------------------------------------- 17b4315306SDan Handley * void plat_secondary_cold_boot_setup(void); 18b4315306SDan Handley * 192bc42067SSandrine Bailleux * In the normal boot flow, cold-booting secondary CPUs is not yet 202bc42067SSandrine Bailleux * implemented and they panic. 212bc42067SSandrine Bailleux * 222bc42067SSandrine Bailleux * When booting an EL3 payload, secondary CPUs are placed in a holding 232bc42067SSandrine Bailleux * pen, waiting for their mailbox to be populated. Note that all CPUs 242bc42067SSandrine Bailleux * share the same mailbox ; therefore, populating it will release all 252bc42067SSandrine Bailleux * CPUs from their holding pen. If finer-grained control is needed then 262bc42067SSandrine Bailleux * this should be handled in the code that secondary CPUs jump to. 272bc42067SSandrine Bailleux * --------------------------------------------------------------------- 28b4315306SDan Handley */ 29b4315306SDan Handleyfunc plat_secondary_cold_boot_setup 302bc42067SSandrine Bailleux#ifndef EL3_PAYLOAD_BASE 312bc42067SSandrine Bailleux /* TODO: Implement secondary CPU cold boot setup on CSS platforms */ 32b4315306SDan Handleycb_panic: 33b4315306SDan Handley b cb_panic 342bc42067SSandrine Bailleux#else 352bc42067SSandrine Bailleux mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE 362bc42067SSandrine Bailleux 372bc42067SSandrine Bailleux /* Wait until the mailbox gets populated */ 382bc42067SSandrine Bailleuxpoll_mailbox: 392bc42067SSandrine Bailleux ldr x1, [x0] 402bc42067SSandrine Bailleux cbz x1, 1f 412bc42067SSandrine Bailleux br x1 422bc42067SSandrine Bailleux1: 432bc42067SSandrine Bailleux wfe 442bc42067SSandrine Bailleux b poll_mailbox 452bc42067SSandrine Bailleux#endif /* EL3_PAYLOAD_BASE */ 46b4315306SDan Handleyendfunc plat_secondary_cold_boot_setup 47b4315306SDan Handley 48804040d1SSandrine Bailleux /* --------------------------------------------------------------------- 494c0d0390SSoby Mathew * uintptr_t plat_get_my_entrypoint (void); 50b4315306SDan Handley * 51804040d1SSandrine Bailleux * Main job of this routine is to distinguish between a cold and a warm 52804040d1SSandrine Bailleux * boot. On CSS platforms, this distinction is based on the contents of 53804040d1SSandrine Bailleux * the Trusted Mailbox. It is initialised to zero by the SCP before the 54804040d1SSandrine Bailleux * AP cores are released from reset. Therefore, a zero mailbox means 55804040d1SSandrine Bailleux * it's a cold reset. 56b4315306SDan Handley * 57804040d1SSandrine Bailleux * This functions returns the contents of the mailbox, i.e.: 58804040d1SSandrine Bailleux * - 0 for a cold boot; 59804040d1SSandrine Bailleux * - the warm boot entrypoint for a warm boot. 60804040d1SSandrine Bailleux * --------------------------------------------------------------------- 61b4315306SDan Handley */ 6238dce70fSSoby Mathewfunc plat_get_my_entrypoint 63785fb92bSSoby Mathew mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE 64804040d1SSandrine Bailleux ldr x0, [x0] 65804040d1SSandrine Bailleux ret 6638dce70fSSoby Mathewendfunc plat_get_my_entrypoint 67b4315306SDan Handley 6838dce70fSSoby Mathew /* ----------------------------------------------------------- 694c0d0390SSoby Mathew * unsigned int css_calc_core_pos_swap_cluster(u_register_t mpidr) 70371d4399SDavid Wang * Utility function to calculate the core position by 7138dce70fSSoby Mathew * swapping the cluster order. This is necessary in order to 7238dce70fSSoby Mathew * match the format of the boot information passed by the SCP 7358523c07SSoby Mathew * and read in plat_is_my_cpu_primary below. 7438dce70fSSoby Mathew * ----------------------------------------------------------- 75b4315306SDan Handley */ 76371d4399SDavid Wangfunc css_calc_core_pos_swap_cluster 77b4315306SDan Handley and x1, x0, #MPIDR_CPU_MASK 78b4315306SDan Handley and x0, x0, #MPIDR_CLUSTER_MASK 79b4315306SDan Handley eor x0, x0, #(1 << MPIDR_AFFINITY_BITS) // swap cluster order 80b4315306SDan Handley add x0, x1, x0, LSR #6 81b4315306SDan Handley ret 82371d4399SDavid Wangendfunc css_calc_core_pos_swap_cluster 83b4315306SDan Handley 84b4315306SDan Handley /* ----------------------------------------------------- 8538dce70fSSoby Mathew * unsigned int plat_is_my_cpu_primary (void); 86b4315306SDan Handley * 8738dce70fSSoby Mathew * Find out whether the current cpu is the primary 88b4315306SDan Handley * cpu (applicable ony after a cold boot) 89b4315306SDan Handley * ----------------------------------------------------- 90b4315306SDan Handley */ 9138dce70fSSoby Mathewfunc plat_is_my_cpu_primary 92b4315306SDan Handley mov x9, x30 9338dce70fSSoby Mathew bl plat_my_core_pos 94b4315306SDan Handley ldr x1, =SCP_BOOT_CFG_ADDR 95b4315306SDan Handley ldr x1, [x1] 968e083ecdSVikram Kanigiri ubfx x1, x1, #PLAT_CSS_PRIMARY_CPU_SHIFT, \ 978e083ecdSVikram Kanigiri #PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 98b4315306SDan Handley cmp x0, x1 9958523c07SSoby Mathew cset w0, eq 100b4315306SDan Handley ret x9 10138dce70fSSoby Mathewendfunc plat_is_my_cpu_primary 102