1b4315306SDan Handley/* 2b4315306SDan Handley * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. 3b4315306SDan Handley * 4b4315306SDan Handley * Redistribution and use in source and binary forms, with or without 5b4315306SDan Handley * modification, are permitted provided that the following conditions are met: 6b4315306SDan Handley * 7b4315306SDan Handley * Redistributions of source code must retain the above copyright notice, this 8b4315306SDan Handley * list of conditions and the following disclaimer. 9b4315306SDan Handley * 10b4315306SDan Handley * Redistributions in binary form must reproduce the above copyright notice, 11b4315306SDan Handley * this list of conditions and the following disclaimer in the documentation 12b4315306SDan Handley * and/or other materials provided with the distribution. 13b4315306SDan Handley * 14b4315306SDan Handley * Neither the name of ARM nor the names of its contributors may be used 15b4315306SDan Handley * to endorse or promote products derived from this software without specific 16b4315306SDan Handley * prior written permission. 17b4315306SDan Handley * 18b4315306SDan Handley * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19b4315306SDan Handley * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20b4315306SDan Handley * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21b4315306SDan Handley * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22b4315306SDan Handley * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23b4315306SDan Handley * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24b4315306SDan Handley * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25b4315306SDan Handley * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26b4315306SDan Handley * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27b4315306SDan Handley * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28b4315306SDan Handley * POSSIBILITY OF SUCH DAMAGE. 29b4315306SDan Handley */ 30b4315306SDan Handley#include <arch.h> 31b4315306SDan Handley#include <asm_macros.S> 32b4315306SDan Handley#include <cpu_macros.S> 33b4315306SDan Handley#include <css_def.h> 34b4315306SDan Handley 35b4315306SDan Handley .weak plat_secondary_cold_boot_setup 3638dce70fSSoby Mathew .weak plat_get_my_entrypoint 37b4315306SDan Handley .weak platform_mem_init 3838dce70fSSoby Mathew .globl plat_arm_calc_core_pos 3938dce70fSSoby Mathew .weak plat_is_my_cpu_primary 40b4315306SDan Handley 41b4315306SDan Handley /* ----------------------------------------------------- 42b4315306SDan Handley * void plat_secondary_cold_boot_setup (void); 43b4315306SDan Handley * 44b4315306SDan Handley * This function performs any platform specific actions 45b4315306SDan Handley * needed for a secondary cpu after a cold reset e.g 46b4315306SDan Handley * mark the cpu's presence, mechanism to place it in a 47b4315306SDan Handley * holding pen etc. 48b4315306SDan Handley * ----------------------------------------------------- 49b4315306SDan Handley */ 50b4315306SDan Handleyfunc plat_secondary_cold_boot_setup 51b4315306SDan Handley /* todo: Implement secondary CPU cold boot setup on CSS platforms */ 52b4315306SDan Handleycb_panic: 53b4315306SDan Handley b cb_panic 54b4315306SDan Handleyendfunc plat_secondary_cold_boot_setup 55b4315306SDan Handley 56*804040d1SSandrine Bailleux /* --------------------------------------------------------------------- 5738dce70fSSoby Mathew * unsigned long plat_get_my_entrypoint (void); 58b4315306SDan Handley * 59*804040d1SSandrine Bailleux * Main job of this routine is to distinguish between a cold and a warm 60*804040d1SSandrine Bailleux * boot. On CSS platforms, this distinction is based on the contents of 61*804040d1SSandrine Bailleux * the Trusted Mailbox. It is initialised to zero by the SCP before the 62*804040d1SSandrine Bailleux * AP cores are released from reset. Therefore, a zero mailbox means 63*804040d1SSandrine Bailleux * it's a cold reset. 64b4315306SDan Handley * 65*804040d1SSandrine Bailleux * This functions returns the contents of the mailbox, i.e.: 66*804040d1SSandrine Bailleux * - 0 for a cold boot; 67*804040d1SSandrine Bailleux * - the warm boot entrypoint for a warm boot. 68*804040d1SSandrine Bailleux * --------------------------------------------------------------------- 69b4315306SDan Handley */ 7038dce70fSSoby Mathewfunc plat_get_my_entrypoint 71*804040d1SSandrine Bailleux mov_imm x0, TRUSTED_MAILBOX_BASE 72*804040d1SSandrine Bailleux ldr x0, [x0] 73*804040d1SSandrine Bailleux ret 7438dce70fSSoby Mathewendfunc plat_get_my_entrypoint 75b4315306SDan Handley 7638dce70fSSoby Mathew /* ----------------------------------------------------------- 7738dce70fSSoby Mathew * unsigned int plat_arm_calc_core_pos(uint64_t mpidr) 7838dce70fSSoby Mathew * Function to calculate the core position by 7938dce70fSSoby Mathew * swapping the cluster order. This is necessary in order to 8038dce70fSSoby Mathew * match the format of the boot information passed by the SCP 8138dce70fSSoby Mathew * and read in platform_is_primary_cpu below. 8238dce70fSSoby Mathew * ----------------------------------------------------------- 83b4315306SDan Handley */ 8438dce70fSSoby Mathewfunc plat_arm_calc_core_pos 85b4315306SDan Handley and x1, x0, #MPIDR_CPU_MASK 86b4315306SDan Handley and x0, x0, #MPIDR_CLUSTER_MASK 87b4315306SDan Handley eor x0, x0, #(1 << MPIDR_AFFINITY_BITS) // swap cluster order 88b4315306SDan Handley add x0, x1, x0, LSR #6 89b4315306SDan Handley ret 9038dce70fSSoby Mathewendfunc plat_arm_calc_core_pos 91b4315306SDan Handley 92b4315306SDan Handley /* ----------------------------------------------------- 93b4315306SDan Handley * void platform_mem_init(void); 94b4315306SDan Handley * 95b4315306SDan Handley * We don't need to carry out any memory initialization 96b4315306SDan Handley * on CSS platforms. The Secure RAM is accessible straight away. 97b4315306SDan Handley * ----------------------------------------------------- 98b4315306SDan Handley */ 99b4315306SDan Handleyfunc platform_mem_init 100b4315306SDan Handley ret 101b4315306SDan Handleyendfunc platform_mem_init 102b4315306SDan Handley 103b4315306SDan Handley /* ----------------------------------------------------- 10438dce70fSSoby Mathew * unsigned int plat_is_my_cpu_primary (void); 105b4315306SDan Handley * 10638dce70fSSoby Mathew * Find out whether the current cpu is the primary 107b4315306SDan Handley * cpu (applicable ony after a cold boot) 108b4315306SDan Handley * ----------------------------------------------------- 109b4315306SDan Handley */ 11038dce70fSSoby Mathewfunc plat_is_my_cpu_primary 111b4315306SDan Handley mov x9, x30 11238dce70fSSoby Mathew bl plat_my_core_pos 113b4315306SDan Handley ldr x1, =SCP_BOOT_CFG_ADDR 114b4315306SDan Handley ldr x1, [x1] 11519af6fceSSoby Mathew ubfx x1, x1, #PRIMARY_CPU_SHIFT, #PRIMARY_CPU_BIT_WIDTH 116b4315306SDan Handley cmp x0, x1 117b4315306SDan Handley cset x0, eq 118b4315306SDan Handley ret x9 11938dce70fSSoby Mathewendfunc plat_is_my_cpu_primary 120