16f249345SYatharth Kochar/* 26f249345SYatharth Kochar * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 36f249345SYatharth Kochar * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 56f249345SYatharth Kochar */ 66f249345SYatharth Kochar#include <arch.h> 76f249345SYatharth Kochar#include <asm_macros.S> 86f249345SYatharth Kochar#include <cpu_macros.S> 96f249345SYatharth Kochar#include <css_def.h> 106f249345SYatharth Kochar 116f249345SYatharth Kochar .weak plat_secondary_cold_boot_setup 126f249345SYatharth Kochar .weak plat_get_my_entrypoint 136f249345SYatharth Kochar .globl css_calc_core_pos_swap_cluster 146f249345SYatharth Kochar .weak plat_is_my_cpu_primary 156f249345SYatharth Kochar 166f249345SYatharth Kochar /* --------------------------------------------------------------------- 176f249345SYatharth Kochar * void plat_secondary_cold_boot_setup(void); 186f249345SYatharth Kochar * In the normal boot flow, cold-booting secondary 196f249345SYatharth Kochar * CPUs is not yet implemented and they panic. 206f249345SYatharth Kochar * --------------------------------------------------------------------- 216f249345SYatharth Kochar */ 226f249345SYatharth Kocharfunc plat_secondary_cold_boot_setup 236f249345SYatharth Kochar /* TODO: Implement secondary CPU cold boot setup on CSS platforms */ 246f249345SYatharth Kocharcb_panic: 256f249345SYatharth Kochar b cb_panic 266f249345SYatharth Kocharendfunc plat_secondary_cold_boot_setup 276f249345SYatharth Kochar 286f249345SYatharth Kochar /* --------------------------------------------------------------------- 296f249345SYatharth Kochar * uintptr_t plat_get_my_entrypoint (void); 306f249345SYatharth Kochar * 316f249345SYatharth Kochar * Main job of this routine is to distinguish between a cold and a warm 326f249345SYatharth Kochar * boot. On CSS platforms, this distinction is based on the contents of 336f249345SYatharth Kochar * the Trusted Mailbox. It is initialised to zero by the SCP before the 346f249345SYatharth Kochar * AP cores are released from reset. Therefore, a zero mailbox means 356f249345SYatharth Kochar * it's a cold reset. 366f249345SYatharth Kochar * 376f249345SYatharth Kochar * This functions returns the contents of the mailbox, i.e.: 386f249345SYatharth Kochar * - 0 for a cold boot; 396f249345SYatharth Kochar * - the warm boot entrypoint for a warm boot. 406f249345SYatharth Kochar * --------------------------------------------------------------------- 416f249345SYatharth Kochar */ 426f249345SYatharth Kocharfunc plat_get_my_entrypoint 436f249345SYatharth Kochar ldr r0, =PLAT_ARM_TRUSTED_MAILBOX_BASE 446f249345SYatharth Kochar ldr r0, [r0] 456f249345SYatharth Kochar bx lr 466f249345SYatharth Kocharendfunc plat_get_my_entrypoint 476f249345SYatharth Kochar 486f249345SYatharth Kochar /* ----------------------------------------------------------- 496f249345SYatharth Kochar * unsigned int css_calc_core_pos_swap_cluster(u_register_t mpidr) 506f249345SYatharth Kochar * Utility function to calculate the core position by 516f249345SYatharth Kochar * swapping the cluster order. This is necessary in order to 526f249345SYatharth Kochar * match the format of the boot information passed by the SCP 536f249345SYatharth Kochar * and read in plat_is_my_cpu_primary below. 546f249345SYatharth Kochar * ----------------------------------------------------------- 556f249345SYatharth Kochar */ 566f249345SYatharth Kocharfunc css_calc_core_pos_swap_cluster 576f249345SYatharth Kochar and r1, r0, #MPIDR_CPU_MASK 586f249345SYatharth Kochar and r0, r0, #MPIDR_CLUSTER_MASK 596f249345SYatharth Kochar eor r0, r0, #(1 << MPIDR_AFFINITY_BITS) // swap cluster order 606f249345SYatharth Kochar add r0, r1, r0, LSR #6 616f249345SYatharth Kochar bx lr 626f249345SYatharth Kocharendfunc css_calc_core_pos_swap_cluster 636f249345SYatharth Kochar 646f249345SYatharth Kochar /* ----------------------------------------------------- 656f249345SYatharth Kochar * unsigned int plat_is_my_cpu_primary (void); 666f249345SYatharth Kochar * 676f249345SYatharth Kochar * Find out whether the current cpu is the primary 686f249345SYatharth Kochar * cpu (applicable ony after a cold boot) 696f249345SYatharth Kochar * ----------------------------------------------------- 706f249345SYatharth Kochar */ 716f249345SYatharth Kocharfunc plat_is_my_cpu_primary 726f249345SYatharth Kochar mov r10, lr 736f249345SYatharth Kochar bl plat_my_core_pos 746f249345SYatharth Kochar ldr r1, =SCP_BOOT_CFG_ADDR 756f249345SYatharth Kochar ldr r1, [r1] 766f249345SYatharth Kochar ubfx r1, r1, #PLAT_CSS_PRIMARY_CPU_SHIFT, \ 776f249345SYatharth Kochar #PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 786f249345SYatharth Kochar cmp r0, r1 796f249345SYatharth Kochar moveq r0, #1 806f249345SYatharth Kochar movne r0, #0 816f249345SYatharth Kochar bx r10 826f249345SYatharth Kocharendfunc plat_is_my_cpu_primary 83