xref: /rk3399_ARM-atf/plat/arm/common/tsp/arm_tsp_setup.c (revision 4c0d03907652fdf9c66a02cec9ea7137ccccd2e9)
1 /*
2  * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * Redistributions of source code must retain the above copyright notice, this
8  * list of conditions and the following disclaimer.
9  *
10  * Redistributions in binary form must reproduce the above copyright notice,
11  * this list of conditions and the following disclaimer in the documentation
12  * and/or other materials provided with the distribution.
13  *
14  * Neither the name of ARM nor the names of its contributors may be used
15  * to endorse or promote products derived from this software without specific
16  * prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28  * POSSIBILITY OF SUCH DAMAGE.
29  */
30 
31 #include <arm_def.h>
32 #include <bl_common.h>
33 #include <console.h>
34 #include <platform_def.h>
35 #include <platform_tsp.h>
36 #include <plat_arm.h>
37 
38 #define BL32_END (unsigned long)(&__BL32_END__)
39 
40 #if USE_COHERENT_MEM
41 /*
42  * The next 2 constants identify the extents of the coherent memory region.
43  * These addresses are used by the MMU setup code and therefore they must be
44  * page-aligned.  It is the responsibility of the linker script to ensure that
45  * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
46  * page-aligned addresses.
47  */
48 #define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
49 #define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
50 #endif
51 
52 
53 /* Weak definitions may be overridden in specific ARM standard platform */
54 #pragma weak tsp_early_platform_setup
55 #pragma weak tsp_platform_setup
56 #pragma weak tsp_plat_arch_setup
57 
58 
59 /*******************************************************************************
60  * Initialize the UART
61  ******************************************************************************/
62 void arm_tsp_early_platform_setup(void)
63 {
64 	/*
65 	 * Initialize a different console than already in use to display
66 	 * messages from TSP
67 	 */
68 	console_init(PLAT_ARM_TSP_UART_BASE, PLAT_ARM_TSP_UART_CLK_IN_HZ,
69 			ARM_CONSOLE_BAUDRATE);
70 }
71 
72 void tsp_early_platform_setup(void)
73 {
74 	arm_tsp_early_platform_setup();
75 }
76 
77 /*******************************************************************************
78  * Perform platform specific setup placeholder
79  ******************************************************************************/
80 void tsp_platform_setup(void)
81 {
82 	plat_arm_gic_driver_init();
83 }
84 
85 /*******************************************************************************
86  * Perform the very early platform specific architectural setup here. At the
87  * moment this is only intializes the MMU
88  ******************************************************************************/
89 void tsp_plat_arch_setup(void)
90 {
91 	arm_setup_page_tables(BL32_BASE,
92 			      (BL32_END - BL32_BASE),
93 			      BL_CODE_BASE,
94 			      BL_CODE_LIMIT,
95 			      BL_RO_DATA_BASE,
96 			      BL_RO_DATA_LIMIT
97 #if USE_COHERENT_MEM
98 			      , BL32_COHERENT_RAM_BASE,
99 			      BL32_COHERENT_RAM_LIMIT
100 #endif
101 			      );
102 	enable_mmu_el1(0);
103 }
104