1b4315306SDan Handley /* 2*c5c54e20SBoyan Karatotev * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3b4315306SDan Handley * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5b4315306SDan Handley */ 6b4315306SDan Handley 7d323af9eSDaniel Boulby #include <assert.h> 809d40e0eSAntonio Nino Diaz 9b4315306SDan Handley #include <platform_def.h> 1009d40e0eSAntonio Nino Diaz 1109d40e0eSAntonio Nino Diaz #include <bl32/tsp/platform_tsp.h> 1209d40e0eSAntonio Nino Diaz #include <common/bl_common.h> 1309d40e0eSAntonio Nino Diaz #include <common/debug.h> 1409d40e0eSAntonio Nino Diaz #include <drivers/arm/pl011.h> 1509d40e0eSAntonio Nino Diaz #include <drivers/console.h> 16bd9344f6SAntonio Nino Diaz #include <plat/arm/common/plat_arm.h> 17*c5c54e20SBoyan Karatotev #include <plat/common/platform.h> 18b4315306SDan Handley 19b4315306SDan Handley /* Weak definitions may be overridden in specific ARM standard platform */ 20b4315306SDan Handley #pragma weak tsp_early_platform_setup 21b4315306SDan Handley #pragma weak tsp_platform_setup 22b4315306SDan Handley #pragma weak tsp_plat_arch_setup 23b4315306SDan Handley 24d323af9eSDaniel Boulby #define MAP_BL_TSP_TOTAL MAP_REGION_FLAT( \ 25d323af9eSDaniel Boulby BL32_BASE, \ 26d323af9eSDaniel Boulby BL32_END - BL32_BASE, \ 27d323af9eSDaniel Boulby MT_MEMORY | MT_RW | MT_SECURE) 28b4315306SDan Handley 29b4315306SDan Handley /******************************************************************************* 30b4315306SDan Handley * Initialize the UART 31b4315306SDan Handley ******************************************************************************/ 32f695e1e0SAndre Przywara static console_t arm_tsp_runtime_console; 3388a0523eSAntonio Nino Diaz 34b4315306SDan Handley void arm_tsp_early_platform_setup(void) 35b4315306SDan Handley { 36b4315306SDan Handley /* 37b4315306SDan Handley * Initialize a different console than already in use to display 38b4315306SDan Handley * messages from TSP 39b4315306SDan Handley */ 4088a0523eSAntonio Nino Diaz int rc = console_pl011_register(PLAT_ARM_TSP_UART_BASE, 4188a0523eSAntonio Nino Diaz PLAT_ARM_TSP_UART_CLK_IN_HZ, 4288a0523eSAntonio Nino Diaz ARM_CONSOLE_BAUDRATE, 4388a0523eSAntonio Nino Diaz &arm_tsp_runtime_console); 4488a0523eSAntonio Nino Diaz if (rc == 0) 4588a0523eSAntonio Nino Diaz panic(); 4688a0523eSAntonio Nino Diaz 47f695e1e0SAndre Przywara console_set_scope(&arm_tsp_runtime_console, 4888a0523eSAntonio Nino Diaz CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); 49b4315306SDan Handley } 50b4315306SDan Handley 51b4315306SDan Handley void tsp_early_platform_setup(void) 52b4315306SDan Handley { 53b4315306SDan Handley arm_tsp_early_platform_setup(); 54b4315306SDan Handley } 55b4315306SDan Handley 56b4315306SDan Handley /******************************************************************************* 57b4315306SDan Handley * Perform platform specific setup placeholder 58b4315306SDan Handley ******************************************************************************/ 59b4315306SDan Handley void tsp_platform_setup(void) 60b4315306SDan Handley { 61*c5c54e20SBoyan Karatotev /* 62*c5c54e20SBoyan Karatotev * On GICv2 the driver must be initialised before calling the plat_ic_* 63*c5c54e20SBoyan Karatotev * functions as they need the data structures. Higher versions don't. 64*c5c54e20SBoyan Karatotev */ 65*c5c54e20SBoyan Karatotev #if USE_GIC_DRIVER == 2 66*c5c54e20SBoyan Karatotev gic_init(plat_my_core_pos()); 67*c5c54e20SBoyan Karatotev #endif 68b4315306SDan Handley } 69b4315306SDan Handley 70b4315306SDan Handley /******************************************************************************* 71b4315306SDan Handley * Perform the very early platform specific architectural setup here. At the 721b491eeaSElyes Haouas * moment this is only initializes the MMU 73b4315306SDan Handley ******************************************************************************/ 74b4315306SDan Handley void tsp_plat_arch_setup(void) 75b4315306SDan Handley { 76b4315306SDan Handley #if USE_COHERENT_MEM 778aabea33SPaul Beesley /* Ensure ARM platforms don't use coherent memory in TSP */ 78d323af9eSDaniel Boulby assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 79b4315306SDan Handley #endif 80d323af9eSDaniel Boulby 81d323af9eSDaniel Boulby const mmap_region_t bl_regions[] = { 82d323af9eSDaniel Boulby MAP_BL_TSP_TOTAL, 832ecaafd2SDaniel Boulby ARM_MAP_BL_RO, 84d323af9eSDaniel Boulby {0} 85d323af9eSDaniel Boulby }; 86d323af9eSDaniel Boulby 870916c38dSRoberto Vargas setup_page_tables(bl_regions, plat_arm_get_mmap()); 88b5fa6563SSandrine Bailleux enable_mmu_el1(0); 8960e8f3cfSPetre-Ionut Tudor 9060e8f3cfSPetre-Ionut Tudor #if PLAT_RO_XLAT_TABLES 9160e8f3cfSPetre-Ionut Tudor arm_xlat_make_tables_readonly(); 9260e8f3cfSPetre-Ionut Tudor #endif 93b4315306SDan Handley } 94