1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <assert.h> 32 #include <console.h> 33 #include <debug.h> 34 #include <mmio.h> 35 #include <plat_arm.h> 36 #include <platform.h> 37 #include <platform_def.h> 38 #include <platform_sp_min.h> 39 40 #define BL32_END (uintptr_t)(&__BL32_END__) 41 42 #if USE_COHERENT_MEM 43 /* 44 * The next 2 constants identify the extents of the coherent memory region. 45 * These addresses are used by the MMU setup code and therefore they must be 46 * page-aligned. It is the responsibility of the linker script to ensure that 47 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 48 * page-aligned addresses. 49 */ 50 #define BL32_COHERENT_RAM_BASE (uintptr_t)(&__COHERENT_RAM_START__) 51 #define BL32_COHERENT_RAM_LIMIT (uintptr_t)(&__COHERENT_RAM_END__) 52 #endif 53 54 55 static entry_point_info_t bl33_image_ep_info; 56 57 /* Weak definitions may be overridden in specific ARM standard platform */ 58 #pragma weak sp_min_early_platform_setup 59 #pragma weak sp_min_platform_setup 60 #pragma weak sp_min_plat_arch_setup 61 62 63 /******************************************************************************* 64 * Return a pointer to the 'entry_point_info' structure of the next image for the 65 * security state specified. BL33 corresponds to the non-secure image type 66 * while BL32 corresponds to the secure image type. A NULL pointer is returned 67 * if the image does not exist. 68 ******************************************************************************/ 69 entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) 70 { 71 entry_point_info_t *next_image_info; 72 73 next_image_info = &bl33_image_ep_info; 74 75 /* 76 * None of the images on the ARM development platforms can have 0x0 77 * as the entrypoint 78 */ 79 if (next_image_info->pc) 80 return next_image_info; 81 else 82 return NULL; 83 } 84 85 /******************************************************************************* 86 * Perform early platform setup. 87 ******************************************************************************/ 88 void arm_sp_min_early_platform_setup(void *from_bl2, 89 void *plat_params_from_bl2) 90 { 91 /* Initialize the console to provide early debug support */ 92 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 93 ARM_CONSOLE_BAUDRATE); 94 95 #if RESET_TO_SP_MIN 96 /* There are no parameters from BL2 if SP_MIN is a reset vector */ 97 assert(from_bl2 == NULL); 98 assert(plat_params_from_bl2 == NULL); 99 100 /* Populate entry point information for BL33 */ 101 SET_PARAM_HEAD(&bl33_image_ep_info, 102 PARAM_EP, 103 VERSION_1, 104 0); 105 /* 106 * Tell SP_MIN where the non-trusted software image 107 * is located and the entry state information 108 */ 109 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 110 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 111 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 112 113 #else /* RESET_TO_SP_MIN */ 114 115 /* 116 * Check params passed from BL2 should not be NULL, 117 */ 118 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 119 assert(params_from_bl2 != NULL); 120 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 121 assert(params_from_bl2->h.version >= VERSION_2); 122 123 bl_params_node_t *bl_params = params_from_bl2->head; 124 125 /* 126 * Copy BL33 entry point information. 127 * They are stored in Secure RAM, in BL2's address space. 128 */ 129 while (bl_params) { 130 if (bl_params->image_id == BL33_IMAGE_ID) { 131 bl33_image_ep_info = *bl_params->ep_info; 132 break; 133 } 134 135 bl_params = bl_params->next_params_info; 136 } 137 138 if (bl33_image_ep_info.pc == 0) 139 panic(); 140 141 #endif /* RESET_TO_SP_MIN */ 142 143 } 144 145 void sp_min_early_platform_setup(void *from_bl2, 146 void *plat_params_from_bl2) 147 { 148 arm_sp_min_early_platform_setup(from_bl2, plat_params_from_bl2); 149 150 /* 151 * Initialize Interconnect for this cluster during cold boot. 152 * No need for locks as no other CPU is active. 153 */ 154 plat_arm_interconnect_init(); 155 156 /* 157 * Enable Interconnect coherency for the primary CPU's cluster. 158 * Earlier bootloader stages might already do this (e.g. Trusted 159 * Firmware's BL1 does it) but we can't assume so. There is no harm in 160 * executing this code twice anyway. 161 * Platform specific PSCI code will enable coherency for other 162 * clusters. 163 */ 164 plat_arm_interconnect_enter_coherency(); 165 } 166 167 /******************************************************************************* 168 * Perform platform specific setup for SP_MIN 169 ******************************************************************************/ 170 void sp_min_platform_setup(void) 171 { 172 /* Initialize the GIC driver, cpu and distributor interfaces */ 173 plat_arm_gic_driver_init(); 174 plat_arm_gic_init(); 175 176 /* 177 * Do initial security configuration to allow DRAM/device access 178 * (if earlier BL has not already done so). 179 */ 180 #if RESET_TO_SP_MIN 181 plat_arm_security_setup(); 182 #endif 183 184 /* Enable and initialize the System level generic timer */ 185 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 186 CNTCR_FCREQ(0) | CNTCR_EN); 187 188 /* Allow access to the System counter timer module */ 189 arm_configure_sys_timer(); 190 191 /* Initialize power controller before setting up topology */ 192 plat_arm_pwrc_setup(); 193 } 194 195 /******************************************************************************* 196 * Perform the very early platform specific architectural setup here. At the 197 * moment this only initializes the MMU 198 ******************************************************************************/ 199 void sp_min_plat_arch_setup(void) 200 { 201 202 arm_setup_page_tables(BL32_BASE, 203 (BL32_END - BL32_BASE), 204 BL_CODE_BASE, 205 BL_CODE_LIMIT, 206 BL_RO_DATA_BASE, 207 BL_RO_DATA_LIMIT 208 #if USE_COHERENT_MEM 209 , BL32_COHERENT_RAM_BASE, 210 BL32_COHERENT_RAM_LIMIT 211 #endif 212 ); 213 214 enable_mmu_secure(0); 215 } 216