1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <assert.h> 32 #include <console.h> 33 #include <mmio.h> 34 #include <plat_arm.h> 35 #include <platform.h> 36 #include <platform_def.h> 37 #include <platform_sp_min.h> 38 39 #define BL32_END (uintptr_t)(&__BL32_END__) 40 41 #if USE_COHERENT_MEM 42 /* 43 * The next 2 constants identify the extents of the coherent memory region. 44 * These addresses are used by the MMU setup code and therefore they must be 45 * page-aligned. It is the responsibility of the linker script to ensure that 46 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 47 * page-aligned addresses. 48 */ 49 #define BL32_COHERENT_RAM_BASE (uintptr_t)(&__COHERENT_RAM_START__) 50 #define BL32_COHERENT_RAM_LIMIT (uintptr_t)(&__COHERENT_RAM_END__) 51 #endif 52 53 54 static entry_point_info_t bl33_image_ep_info; 55 56 /* Weak definitions may be overridden in specific ARM standard platform */ 57 #pragma weak sp_min_early_platform_setup 58 #pragma weak sp_min_platform_setup 59 #pragma weak sp_min_plat_arch_setup 60 61 #ifndef RESET_TO_SP_MIN 62 #error (" RESET_TO_SP_MIN flag is expected to be set.") 63 #endif 64 65 66 /******************************************************************************* 67 * Return a pointer to the 'entry_point_info' structure of the next image for the 68 * security state specified. BL33 corresponds to the non-secure image type 69 * while BL32 corresponds to the secure image type. A NULL pointer is returned 70 * if the image does not exist. 71 ******************************************************************************/ 72 entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) 73 { 74 entry_point_info_t *next_image_info; 75 76 next_image_info = &bl33_image_ep_info; 77 78 /* 79 * None of the images on the ARM development platforms can have 0x0 80 * as the entrypoint 81 */ 82 if (next_image_info->pc) 83 return next_image_info; 84 else 85 return NULL; 86 } 87 88 /******************************************************************************* 89 * Perform early platform setup. We expect SP_MIN is the first boot loader 90 * image and RESET_TO_SP_MIN build option to be set. 91 ******************************************************************************/ 92 void arm_sp_min_early_platform_setup(void) 93 { 94 /* Initialize the console to provide early debug support */ 95 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 96 ARM_CONSOLE_BAUDRATE); 97 98 /* Populate entry point information for BL33 */ 99 SET_PARAM_HEAD(&bl33_image_ep_info, 100 PARAM_EP, 101 VERSION_1, 102 0); 103 /* 104 * Tell SP_MIN where the non-trusted software image 105 * is located and the entry state information 106 */ 107 #ifdef PRELOADED_BL33_BASE 108 bl33_image_ep_info.pc = PRELOADED_BL33_BASE; 109 #else 110 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 111 #endif 112 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 113 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 114 } 115 116 void sp_min_early_platform_setup(void) 117 { 118 arm_sp_min_early_platform_setup(); 119 120 /* 121 * Initialize Interconnect for this cluster during cold boot. 122 * No need for locks as no other CPU is active. 123 */ 124 plat_arm_interconnect_init(); 125 126 /* 127 * Enable Interconnect coherency for the primary CPU's cluster. 128 * Earlier bootloader stages might already do this (e.g. Trusted 129 * Firmware's BL1 does it) but we can't assume so. There is no harm in 130 * executing this code twice anyway. 131 * Platform specific PSCI code will enable coherency for other 132 * clusters. 133 */ 134 plat_arm_interconnect_enter_coherency(); 135 } 136 137 /******************************************************************************* 138 * Perform platform specific setup for SP_MIN 139 ******************************************************************************/ 140 void sp_min_platform_setup(void) 141 { 142 /* Initialize the GIC driver, cpu and distributor interfaces */ 143 plat_arm_gic_driver_init(); 144 plat_arm_gic_init(); 145 146 /* 147 * Do initial security configuration to allow DRAM/device access 148 * (if earlier BL has not already done so). 149 * TODO: If RESET_TO_SP_MIN is not set, the security setup needs 150 * to be skipped. 151 */ 152 plat_arm_security_setup(); 153 154 /* Enable and initialize the System level generic timer */ 155 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 156 CNTCR_FCREQ(0) | CNTCR_EN); 157 158 /* Allow access to the System counter timer module */ 159 arm_configure_sys_timer(); 160 161 /* Initialize power controller before setting up topology */ 162 plat_arm_pwrc_setup(); 163 } 164 165 /******************************************************************************* 166 * Perform the very early platform specific architectural setup here. At the 167 * moment this only initializes the MMU 168 ******************************************************************************/ 169 void sp_min_plat_arch_setup(void) 170 { 171 172 arm_setup_page_tables(BL32_BASE, 173 (BL32_END - BL32_BASE), 174 BL_CODE_BASE, 175 BL_CODE_LIMIT, 176 BL_RO_DATA_BASE, 177 BL_RO_DATA_LIMIT 178 #if USE_COHERENT_MEM 179 , BL32_COHERENT_RAM_BASE, 180 BL32_COHERENT_RAM_LIMIT 181 #endif 182 ); 183 184 enable_mmu_secure(0); 185 } 186