1 /* 2 * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <bl32/sp_min/platform_sp_min.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <drivers/console.h> 15 #include <lib/mmio.h> 16 #include <plat/arm/common/plat_arm.h> 17 #include <plat/common/platform.h> 18 19 static entry_point_info_t bl33_image_ep_info; 20 21 /* Weak definitions may be overridden in specific ARM standard platform */ 22 #pragma weak sp_min_platform_setup 23 #pragma weak sp_min_plat_arch_setup 24 #pragma weak plat_arm_sp_min_early_platform_setup 25 26 #define MAP_BL_SP_MIN_TOTAL MAP_REGION_FLAT( \ 27 BL32_BASE, \ 28 BL32_END - BL32_BASE, \ 29 MT_MEMORY | MT_RW | MT_SECURE) 30 31 /* 32 * Check that BL32_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page 33 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. 34 */ 35 #if !RESET_TO_SP_MIN 36 CASSERT(BL32_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl32_base_overflows); 37 #endif 38 39 /******************************************************************************* 40 * Return a pointer to the 'entry_point_info' structure of the next image for the 41 * security state specified. BL33 corresponds to the non-secure image type 42 * while BL32 corresponds to the secure image type. A NULL pointer is returned 43 * if the image does not exist. 44 ******************************************************************************/ 45 entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) 46 { 47 entry_point_info_t *next_image_info; 48 49 next_image_info = &bl33_image_ep_info; 50 51 /* 52 * None of the images on the ARM development platforms can have 0x0 53 * as the entrypoint 54 */ 55 if (next_image_info->pc) 56 return next_image_info; 57 else 58 return NULL; 59 } 60 61 /******************************************************************************* 62 * Utility function to perform early platform setup. 63 ******************************************************************************/ 64 void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config, 65 uintptr_t hw_config, void *plat_params_from_bl2) 66 { 67 /* Initialize the console to provide early debug support */ 68 arm_console_boot_init(); 69 70 #if RESET_TO_SP_MIN 71 /* There are no parameters from BL2 if SP_MIN is a reset vector */ 72 assert(from_bl2 == NULL); 73 assert(plat_params_from_bl2 == NULL); 74 75 /* Populate entry point information for BL33 */ 76 SET_PARAM_HEAD(&bl33_image_ep_info, 77 PARAM_EP, 78 VERSION_1, 79 0); 80 /* 81 * Tell SP_MIN where the non-trusted software image 82 * is located and the entry state information 83 */ 84 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 85 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 86 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 87 88 # if ARM_LINUX_KERNEL_AS_BL33 89 /* 90 * According to the file ``Documentation/arm/Booting`` of the Linux 91 * kernel tree, Linux expects: 92 * r0 = 0 93 * r1 = machine type number, optional in DT-only platforms (~0 if so) 94 * r2 = Physical address of the device tree blob 95 */ 96 bl33_image_ep_info.args.arg0 = 0U; 97 bl33_image_ep_info.args.arg1 = ~0U; 98 bl33_image_ep_info.args.arg2 = (u_register_t)ARM_PRELOADED_DTB_BASE; 99 # endif 100 101 #else /* RESET_TO_SP_MIN */ 102 103 /* 104 * Check params passed from BL2 should not be NULL, 105 */ 106 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 107 assert(params_from_bl2 != NULL); 108 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 109 assert(params_from_bl2->h.version >= VERSION_2); 110 111 bl_params_node_t *bl_params = params_from_bl2->head; 112 113 /* 114 * Copy BL33 entry point information. 115 * They are stored in Secure RAM, in BL2's address space. 116 */ 117 while (bl_params) { 118 if (bl_params->image_id == BL33_IMAGE_ID) { 119 bl33_image_ep_info = *bl_params->ep_info; 120 break; 121 } 122 123 bl_params = bl_params->next_params_info; 124 } 125 126 if (bl33_image_ep_info.pc == 0) 127 panic(); 128 129 #endif /* RESET_TO_SP_MIN */ 130 131 } 132 133 /******************************************************************************* 134 * Default implementation for sp_min_platform_setup2() for ARM platforms 135 ******************************************************************************/ 136 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 137 u_register_t arg2, u_register_t arg3) 138 { 139 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 140 141 /* 142 * Initialize Interconnect for this cluster during cold boot. 143 * No need for locks as no other CPU is active. 144 */ 145 plat_arm_interconnect_init(); 146 147 /* 148 * Enable Interconnect coherency for the primary CPU's cluster. 149 * Earlier bootloader stages might already do this (e.g. Trusted 150 * Firmware's BL1 does it) but we can't assume so. There is no harm in 151 * executing this code twice anyway. 152 * Platform specific PSCI code will enable coherency for other 153 * clusters. 154 */ 155 plat_arm_interconnect_enter_coherency(); 156 } 157 158 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, 159 u_register_t arg2, u_register_t arg3) 160 { 161 plat_arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); 162 } 163 164 /******************************************************************************* 165 * Perform any SP_MIN platform runtime setup prior to SP_MIN exit. 166 * Common to ARM standard platforms. 167 ******************************************************************************/ 168 void arm_sp_min_plat_runtime_setup(void) 169 { 170 /* Initialize the runtime console */ 171 arm_console_runtime_init(); 172 173 #if PLAT_RO_XLAT_TABLES 174 arm_xlat_make_tables_readonly(); 175 #endif 176 } 177 178 /******************************************************************************* 179 * Perform platform specific setup for SP_MIN 180 ******************************************************************************/ 181 void sp_min_platform_setup(void) 182 { 183 /* Initialize the GIC driver, cpu and distributor interfaces */ 184 plat_arm_gic_driver_init(); 185 plat_arm_gic_init(); 186 187 /* 188 * Do initial security configuration to allow DRAM/device access 189 * (if earlier BL has not already done so). 190 */ 191 #if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME 192 plat_arm_security_setup(); 193 194 #if defined(PLAT_ARM_MEM_PROT_ADDR) 195 arm_nor_psci_do_dyn_mem_protect(); 196 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 197 198 #endif 199 200 /* Enable and initialize the System level generic timer */ 201 #ifdef ARM_SYS_CNTCTL_BASE 202 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 203 CNTCR_FCREQ(0U) | CNTCR_EN); 204 #endif 205 #ifdef ARM_SYS_TIMCTL_BASE 206 /* Allow access to the System counter timer module */ 207 arm_configure_sys_timer(); 208 #endif 209 /* Initialize power controller before setting up topology */ 210 plat_arm_pwrc_setup(); 211 } 212 213 void sp_min_plat_runtime_setup(void) 214 { 215 arm_sp_min_plat_runtime_setup(); 216 } 217 218 /******************************************************************************* 219 * Perform the very early platform specific architectural setup here. At the 220 * moment this only initializes the MMU 221 ******************************************************************************/ 222 void arm_sp_min_plat_arch_setup(void) 223 { 224 const mmap_region_t bl_regions[] = { 225 MAP_BL_SP_MIN_TOTAL, 226 ARM_MAP_BL_RO, 227 #if USE_COHERENT_MEM 228 ARM_MAP_BL_COHERENT_RAM, 229 #endif 230 {0} 231 }; 232 233 setup_page_tables(bl_regions, plat_arm_get_mmap()); 234 235 enable_mmu_svc_mon(0); 236 } 237 238 void sp_min_plat_arch_setup(void) 239 { 240 arm_sp_min_plat_arch_setup(); 241 } 242