1 /* 2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <bl_common.h> 9 #include <console.h> 10 #include <debug.h> 11 #include <mmio.h> 12 #include <plat_arm.h> 13 #include <platform.h> 14 #include <platform_def.h> 15 #include <platform_sp_min.h> 16 17 static entry_point_info_t bl33_image_ep_info; 18 19 /* Weak definitions may be overridden in specific ARM standard platform */ 20 #pragma weak sp_min_platform_setup 21 #pragma weak sp_min_plat_arch_setup 22 #pragma weak plat_arm_sp_min_early_platform_setup 23 24 #define MAP_BL_SP_MIN_TOTAL MAP_REGION_FLAT( \ 25 BL32_BASE, \ 26 BL32_END - BL32_BASE, \ 27 MT_MEMORY | MT_RW | MT_SECURE) 28 29 /* 30 * Check that BL32_BASE is above ARM_TB_FW_CONFIG_LIMIT. The reserved page 31 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. 32 */ 33 CASSERT(BL32_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl32_base_overflows); 34 35 /******************************************************************************* 36 * Return a pointer to the 'entry_point_info' structure of the next image for the 37 * security state specified. BL33 corresponds to the non-secure image type 38 * while BL32 corresponds to the secure image type. A NULL pointer is returned 39 * if the image does not exist. 40 ******************************************************************************/ 41 entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) 42 { 43 entry_point_info_t *next_image_info; 44 45 next_image_info = &bl33_image_ep_info; 46 47 /* 48 * None of the images on the ARM development platforms can have 0x0 49 * as the entrypoint 50 */ 51 if (next_image_info->pc) 52 return next_image_info; 53 else 54 return NULL; 55 } 56 57 /******************************************************************************* 58 * Utility function to perform early platform setup. 59 ******************************************************************************/ 60 void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config, 61 uintptr_t hw_config, void *plat_params_from_bl2) 62 { 63 /* Initialize the console to provide early debug support */ 64 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 65 ARM_CONSOLE_BAUDRATE); 66 67 #if RESET_TO_SP_MIN 68 /* There are no parameters from BL2 if SP_MIN is a reset vector */ 69 assert(from_bl2 == NULL); 70 assert(plat_params_from_bl2 == NULL); 71 72 /* Populate entry point information for BL33 */ 73 SET_PARAM_HEAD(&bl33_image_ep_info, 74 PARAM_EP, 75 VERSION_1, 76 0); 77 /* 78 * Tell SP_MIN where the non-trusted software image 79 * is located and the entry state information 80 */ 81 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 82 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 83 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 84 85 #else /* RESET_TO_SP_MIN */ 86 87 /* 88 * Check params passed from BL2 should not be NULL, 89 */ 90 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 91 assert(params_from_bl2 != NULL); 92 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 93 assert(params_from_bl2->h.version >= VERSION_2); 94 95 bl_params_node_t *bl_params = params_from_bl2->head; 96 97 /* 98 * Copy BL33 entry point information. 99 * They are stored in Secure RAM, in BL2's address space. 100 */ 101 while (bl_params) { 102 if (bl_params->image_id == BL33_IMAGE_ID) { 103 bl33_image_ep_info = *bl_params->ep_info; 104 break; 105 } 106 107 bl_params = bl_params->next_params_info; 108 } 109 110 if (bl33_image_ep_info.pc == 0) 111 panic(); 112 113 #endif /* RESET_TO_SP_MIN */ 114 115 } 116 117 /******************************************************************************* 118 * Default implementation for sp_min_platform_setup2() for ARM platforms 119 ******************************************************************************/ 120 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 121 u_register_t arg2, u_register_t arg3) 122 { 123 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 124 125 /* 126 * Initialize Interconnect for this cluster during cold boot. 127 * No need for locks as no other CPU is active. 128 */ 129 plat_arm_interconnect_init(); 130 131 /* 132 * Enable Interconnect coherency for the primary CPU's cluster. 133 * Earlier bootloader stages might already do this (e.g. Trusted 134 * Firmware's BL1 does it) but we can't assume so. There is no harm in 135 * executing this code twice anyway. 136 * Platform specific PSCI code will enable coherency for other 137 * clusters. 138 */ 139 plat_arm_interconnect_enter_coherency(); 140 } 141 142 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, 143 u_register_t arg2, u_register_t arg3) 144 { 145 plat_arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); 146 } 147 148 /******************************************************************************* 149 * Perform any SP_MIN platform runtime setup prior to SP_MIN exit. 150 * Common to ARM standard platforms. 151 ******************************************************************************/ 152 void arm_sp_min_plat_runtime_setup(void) 153 { 154 /* Initialize the runtime console */ 155 console_init(PLAT_ARM_SP_MIN_RUN_UART_BASE, 156 PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ, ARM_CONSOLE_BAUDRATE); 157 } 158 159 /******************************************************************************* 160 * Perform platform specific setup for SP_MIN 161 ******************************************************************************/ 162 void sp_min_platform_setup(void) 163 { 164 /* Initialize the GIC driver, cpu and distributor interfaces */ 165 plat_arm_gic_driver_init(); 166 plat_arm_gic_init(); 167 168 /* 169 * Do initial security configuration to allow DRAM/device access 170 * (if earlier BL has not already done so). 171 */ 172 #if RESET_TO_SP_MIN 173 plat_arm_security_setup(); 174 175 #if defined(PLAT_ARM_MEM_PROT_ADDR) 176 arm_nor_psci_do_dyn_mem_protect(); 177 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 178 179 #endif 180 181 /* Enable and initialize the System level generic timer */ 182 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 183 CNTCR_FCREQ(0U) | CNTCR_EN); 184 185 /* Allow access to the System counter timer module */ 186 arm_configure_sys_timer(); 187 188 /* Initialize power controller before setting up topology */ 189 plat_arm_pwrc_setup(); 190 } 191 192 void sp_min_plat_runtime_setup(void) 193 { 194 arm_sp_min_plat_runtime_setup(); 195 } 196 197 /******************************************************************************* 198 * Perform the very early platform specific architectural setup here. At the 199 * moment this only initializes the MMU 200 ******************************************************************************/ 201 void sp_min_plat_arch_setup(void) 202 { 203 const mmap_region_t bl_regions[] = { 204 MAP_BL_SP_MIN_TOTAL, 205 ARM_MAP_BL_RO, 206 #if USE_COHERENT_MEM 207 ARM_MAP_BL_COHERENT_RAM, 208 #endif 209 {0} 210 }; 211 212 arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); 213 214 enable_mmu_svc_mon(0); 215 } 216