1 /* 2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <console.h> 9 #include <debug.h> 10 #include <mmio.h> 11 #include <plat_arm.h> 12 #include <platform.h> 13 #include <platform_def.h> 14 #include <platform_sp_min.h> 15 16 #define BL32_END (uintptr_t)(&__BL32_END__) 17 18 static entry_point_info_t bl33_image_ep_info; 19 20 /* Weak definitions may be overridden in specific ARM standard platform */ 21 #pragma weak sp_min_platform_setup 22 #pragma weak sp_min_plat_arch_setup 23 #pragma weak plat_arm_sp_min_early_platform_setup 24 25 #define MAP_BL_SP_MIN_TOTAL MAP_REGION_FLAT( \ 26 BL32_BASE, \ 27 BL32_END - BL32_BASE, \ 28 MT_MEMORY | MT_RW | MT_SECURE) 29 30 /* 31 * Check that BL32_BASE is above ARM_TB_FW_CONFIG_LIMIT. The reserved page 32 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. 33 */ 34 CASSERT(BL32_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl32_base_overflows); 35 36 /******************************************************************************* 37 * Return a pointer to the 'entry_point_info' structure of the next image for the 38 * security state specified. BL33 corresponds to the non-secure image type 39 * while BL32 corresponds to the secure image type. A NULL pointer is returned 40 * if the image does not exist. 41 ******************************************************************************/ 42 entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) 43 { 44 entry_point_info_t *next_image_info; 45 46 next_image_info = &bl33_image_ep_info; 47 48 /* 49 * None of the images on the ARM development platforms can have 0x0 50 * as the entrypoint 51 */ 52 if (next_image_info->pc) 53 return next_image_info; 54 else 55 return NULL; 56 } 57 58 /******************************************************************************* 59 * Utility function to perform early platform setup. 60 ******************************************************************************/ 61 void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config, 62 uintptr_t hw_config, void *plat_params_from_bl2) 63 { 64 /* Initialize the console to provide early debug support */ 65 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 66 ARM_CONSOLE_BAUDRATE); 67 68 #if RESET_TO_SP_MIN 69 /* There are no parameters from BL2 if SP_MIN is a reset vector */ 70 assert(from_bl2 == NULL); 71 assert(plat_params_from_bl2 == NULL); 72 73 /* Populate entry point information for BL33 */ 74 SET_PARAM_HEAD(&bl33_image_ep_info, 75 PARAM_EP, 76 VERSION_1, 77 0); 78 /* 79 * Tell SP_MIN where the non-trusted software image 80 * is located and the entry state information 81 */ 82 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 83 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 84 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 85 86 #else /* RESET_TO_SP_MIN */ 87 88 /* 89 * Check params passed from BL2 should not be NULL, 90 */ 91 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 92 assert(params_from_bl2 != NULL); 93 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 94 assert(params_from_bl2->h.version >= VERSION_2); 95 96 bl_params_node_t *bl_params = params_from_bl2->head; 97 98 /* 99 * Copy BL33 entry point information. 100 * They are stored in Secure RAM, in BL2's address space. 101 */ 102 while (bl_params) { 103 if (bl_params->image_id == BL33_IMAGE_ID) { 104 bl33_image_ep_info = *bl_params->ep_info; 105 break; 106 } 107 108 bl_params = bl_params->next_params_info; 109 } 110 111 if (bl33_image_ep_info.pc == 0) 112 panic(); 113 114 #endif /* RESET_TO_SP_MIN */ 115 116 } 117 118 /******************************************************************************* 119 * Default implementation for sp_min_platform_setup2() for ARM platforms 120 ******************************************************************************/ 121 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 122 u_register_t arg2, u_register_t arg3) 123 { 124 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 125 126 /* 127 * Initialize Interconnect for this cluster during cold boot. 128 * No need for locks as no other CPU is active. 129 */ 130 plat_arm_interconnect_init(); 131 132 /* 133 * Enable Interconnect coherency for the primary CPU's cluster. 134 * Earlier bootloader stages might already do this (e.g. Trusted 135 * Firmware's BL1 does it) but we can't assume so. There is no harm in 136 * executing this code twice anyway. 137 * Platform specific PSCI code will enable coherency for other 138 * clusters. 139 */ 140 plat_arm_interconnect_enter_coherency(); 141 } 142 143 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, 144 u_register_t arg2, u_register_t arg3) 145 { 146 plat_arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); 147 } 148 149 /******************************************************************************* 150 * Perform any SP_MIN platform runtime setup prior to SP_MIN exit. 151 * Common to ARM standard platforms. 152 ******************************************************************************/ 153 void arm_sp_min_plat_runtime_setup(void) 154 { 155 /* Initialize the runtime console */ 156 console_init(PLAT_ARM_SP_MIN_RUN_UART_BASE, 157 PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ, ARM_CONSOLE_BAUDRATE); 158 } 159 160 /******************************************************************************* 161 * Perform platform specific setup for SP_MIN 162 ******************************************************************************/ 163 void sp_min_platform_setup(void) 164 { 165 /* Initialize the GIC driver, cpu and distributor interfaces */ 166 plat_arm_gic_driver_init(); 167 plat_arm_gic_init(); 168 169 /* 170 * Do initial security configuration to allow DRAM/device access 171 * (if earlier BL has not already done so). 172 */ 173 #if RESET_TO_SP_MIN 174 plat_arm_security_setup(); 175 176 #if defined(PLAT_ARM_MEM_PROT_ADDR) 177 arm_nor_psci_do_dyn_mem_protect(); 178 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 179 180 #endif 181 182 /* Enable and initialize the System level generic timer */ 183 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 184 CNTCR_FCREQ(0) | CNTCR_EN); 185 186 /* Allow access to the System counter timer module */ 187 arm_configure_sys_timer(); 188 189 /* Initialize power controller before setting up topology */ 190 plat_arm_pwrc_setup(); 191 } 192 193 void sp_min_plat_runtime_setup(void) 194 { 195 arm_sp_min_plat_runtime_setup(); 196 } 197 198 /******************************************************************************* 199 * Perform the very early platform specific architectural setup here. At the 200 * moment this only initializes the MMU 201 ******************************************************************************/ 202 void sp_min_plat_arch_setup(void) 203 { 204 const mmap_region_t bl_regions[] = { 205 MAP_BL_SP_MIN_TOTAL, 206 ARM_MAP_BL_RO, 207 #if USE_COHERENT_MEM 208 ARM_MAP_BL_COHERENT_RAM, 209 #endif 210 {0} 211 }; 212 213 arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); 214 215 enable_mmu_svc_mon(0); 216 } 217