1 /* 2 * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <bl32/sp_min/platform_sp_min.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <drivers/console.h> 15 #include <lib/mmio.h> 16 #include <plat/arm/common/plat_arm.h> 17 #include <plat/common/platform.h> 18 19 struct transfer_list_header *secure_tl; 20 struct transfer_list_header *ns_tl __unused; 21 22 static entry_point_info_t bl33_image_ep_info; 23 24 /* Weak definitions may be overridden in specific ARM standard platform */ 25 #pragma weak sp_min_platform_setup 26 #pragma weak sp_min_plat_arch_setup 27 #pragma weak plat_arm_sp_min_early_platform_setup 28 29 #define MAP_BL_SP_MIN_TOTAL MAP_REGION_FLAT( \ 30 BL32_BASE, \ 31 BL32_END - BL32_BASE, \ 32 MT_MEMORY | MT_RW | MT_SECURE) 33 34 #define MAP_EL3_FW_HANDOFF \ 35 MAP_REGION_FLAT(PLAT_ARM_EL3_FW_HANDOFF_BASE, \ 36 PLAT_ARM_FW_HANDOFF_SIZE, MT_MEMORY | MT_RW | EL3_PAS) 37 38 #define MAP_FW_NS_HANDOFF \ 39 MAP_REGION_FLAT(FW_NS_HANDOFF_BASE, PLAT_ARM_FW_HANDOFF_SIZE, \ 40 MT_MEMORY | MT_RW | MT_NS) 41 42 /* 43 * Check that BL32_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page 44 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. 45 */ 46 #if !RESET_TO_SP_MIN 47 #if TRANSFER_LIST 48 CASSERT(BL32_BASE >= PLAT_ARM_EL3_FW_HANDOFF_LIMIT, assert_bl32_base_overflows); 49 #else 50 CASSERT(BL32_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl32_base_overflows); 51 #endif 52 #endif 53 54 /******************************************************************************* 55 * Return a pointer to the 'entry_point_info' structure of the next image for the 56 * security state specified. BL33 corresponds to the non-secure image type 57 * while BL32 corresponds to the secure image type. A NULL pointer is returned 58 * if the image does not exist. 59 ******************************************************************************/ 60 entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) 61 { 62 entry_point_info_t *next_image_info; 63 64 next_image_info = &bl33_image_ep_info; 65 66 /* 67 * None of the images on the ARM development platforms can have 0x0 68 * as the entrypoint 69 */ 70 if (next_image_info->pc) 71 return next_image_info; 72 else 73 return NULL; 74 } 75 76 /******************************************************************************* 77 * Utility function to perform early platform setup. 78 ******************************************************************************/ 79 void arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 80 u_register_t arg2, u_register_t arg3) 81 { 82 struct transfer_list_entry *te __unused; 83 84 /* Initialize the console to provide early debug support */ 85 arm_console_boot_init(); 86 87 #if TRANSFER_LIST 88 secure_tl = (struct transfer_list_header *)arg3; 89 90 te = transfer_list_find(secure_tl, TL_TAG_EXEC_EP_INFO32); 91 assert(te != NULL); 92 93 bl33_image_ep_info = 94 *(struct entry_point_info *)transfer_list_entry_data(te); 95 return; 96 #endif /* TRANSFER_LIST */ 97 98 #if RESET_TO_SP_MIN 99 /* Populate entry point information for BL33 */ 100 SET_PARAM_HEAD(&bl33_image_ep_info, 101 PARAM_EP, 102 VERSION_1, 103 0); 104 /* 105 * Tell SP_MIN where the non-trusted software image 106 * is located and the entry state information 107 */ 108 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 109 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 110 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 111 112 #if ARM_LINUX_KERNEL_AS_BL33 113 /* 114 * According to the file ``Documentation/arm/Booting`` of the Linux 115 * kernel tree, Linux expects: 116 * r0 = 0 117 * r1 = machine type number, optional in DT-only platforms (~0 if so) 118 * r2 = Physical address of the device tree blob 119 */ 120 bl33_image_ep_info.args.arg0 = 0U; 121 bl33_image_ep_info.args.arg1 = ~0U; 122 bl33_image_ep_info.args.arg2 = (u_register_t)ARM_PRELOADED_DTB_BASE; 123 # endif 124 125 #else /* RESET_TO_SP_MIN */ 126 127 /* 128 * Check params passed from BL2 should not be NULL, 129 */ 130 bl_params_t *params_from_bl2 = (bl_params_t *)arg0; 131 assert(params_from_bl2 != NULL); 132 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 133 assert(params_from_bl2->h.version >= VERSION_2); 134 135 bl_params_node_t *bl_params = params_from_bl2->head; 136 137 /* 138 * Copy BL33 entry point information. 139 * They are stored in Secure RAM, in BL2's address space. 140 */ 141 while (bl_params) { 142 if (bl_params->image_id == BL33_IMAGE_ID) { 143 bl33_image_ep_info = *bl_params->ep_info; 144 break; 145 } 146 147 bl_params = bl_params->next_params_info; 148 } 149 150 if (bl33_image_ep_info.pc == 0) 151 panic(); 152 153 #endif /* RESET_TO_SP_MIN */ 154 155 } 156 157 /******************************************************************************* 158 * Default implementation for sp_min_platform_setup2() for ARM platforms 159 ******************************************************************************/ 160 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 161 u_register_t arg2, u_register_t arg3) 162 { 163 arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); 164 165 /* 166 * Initialize Interconnect for this cluster during cold boot. 167 * No need for locks as no other CPU is active. 168 */ 169 plat_arm_interconnect_init(); 170 171 /* 172 * Enable Interconnect coherency for the primary CPU's cluster. 173 * Earlier bootloader stages might already do this (e.g. Trusted 174 * Firmware's BL1 does it) but we can't assume so. There is no harm in 175 * executing this code twice anyway. 176 * Platform specific PSCI code will enable coherency for other 177 * clusters. 178 */ 179 plat_arm_interconnect_enter_coherency(); 180 } 181 182 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, 183 u_register_t arg2, u_register_t arg3) 184 { 185 plat_arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); 186 } 187 188 /******************************************************************************* 189 * Perform any SP_MIN platform runtime setup prior to SP_MIN exit. 190 * Common to ARM standard platforms. 191 ******************************************************************************/ 192 void arm_sp_min_plat_runtime_setup(void) 193 { 194 /* Initialize the runtime console */ 195 arm_console_runtime_init(); 196 197 #if PLAT_RO_XLAT_TABLES 198 arm_xlat_make_tables_readonly(); 199 #endif 200 } 201 202 /******************************************************************************* 203 * Perform platform specific setup for SP_MIN 204 ******************************************************************************/ 205 void sp_min_platform_setup(void) 206 { 207 struct transfer_list_entry *te __unused; 208 209 /* Initialize the GIC driver, cpu and distributor interfaces */ 210 unsigned int core_pos = plat_my_core_pos(); 211 212 gic_init(core_pos); 213 gic_pcpu_init(core_pos); 214 gic_cpuif_enable(core_pos); 215 216 #if TRANSFER_LIST 217 ns_tl = transfer_list_ensure((void *)FW_NS_HANDOFF_BASE, 218 PLAT_ARM_FW_HANDOFF_SIZE); 219 if (ns_tl == NULL) { 220 ERROR("Non-secure transfer list initialisation failed!\n"); 221 panic(); 222 } 223 224 te = transfer_list_find(secure_tl, TL_TAG_FDT); 225 if (te != NULL) { 226 te = transfer_list_add(ns_tl, TL_TAG_FDT, te->data_size, 227 (void *)transfer_list_entry_data(te)); 228 if (te == NULL) { 229 ERROR("Failed to relocate device tree into non-secure memory.\n"); 230 panic(); 231 } 232 } 233 234 transfer_list_set_handoff_args(ns_tl, &bl33_image_ep_info); 235 #endif 236 237 /* 238 * Do initial security configuration to allow DRAM/device access 239 * (if earlier BL has not already done so). 240 */ 241 #if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME 242 plat_arm_security_setup(); 243 244 #if defined(PLAT_ARM_MEM_PROT_ADDR) 245 arm_nor_psci_do_dyn_mem_protect(); 246 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 247 248 #endif 249 250 /* Enable and initialize the System level generic timer */ 251 #ifdef ARM_SYS_CNTCTL_BASE 252 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 253 CNTCR_FCREQ(0U) | CNTCR_EN); 254 #endif 255 #ifdef ARM_SYS_TIMCTL_BASE 256 /* Allow access to the System counter timer module */ 257 arm_configure_sys_timer(); 258 #endif 259 /* Initialize power controller before setting up topology */ 260 plat_arm_pwrc_setup(); 261 } 262 263 void sp_min_plat_runtime_setup(void) 264 { 265 arm_sp_min_plat_runtime_setup(); 266 } 267 268 /******************************************************************************* 269 * Perform the very early platform specific architectural setup here. At the 270 * moment this only initializes the MMU 271 ******************************************************************************/ 272 void arm_sp_min_plat_arch_setup(void) 273 { 274 const mmap_region_t bl_regions[] = { 275 MAP_BL_SP_MIN_TOTAL, 276 ARM_MAP_BL_RO, 277 #if USE_COHERENT_MEM 278 ARM_MAP_BL_COHERENT_RAM, 279 #endif 280 #if TRANSFER_LIST 281 MAP_EL3_FW_HANDOFF, 282 MAP_FW_NS_HANDOFF, 283 #endif 284 {0} 285 }; 286 287 setup_page_tables(bl_regions, plat_arm_get_mmap()); 288 289 enable_mmu_svc_mon(0); 290 } 291 292 void sp_min_plat_arch_setup(void) 293 { 294 arm_sp_min_plat_arch_setup(); 295 } 296