1618f0feeSVikram Kanigiri /* 223411d2cSSummer Qin * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3618f0feeSVikram Kanigiri * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5618f0feeSVikram Kanigiri */ 6618f0feeSVikram Kanigiri 7618f0feeSVikram Kanigiri #include <arm_def.h> 8618f0feeSVikram Kanigiri #include <assert.h> 9618f0feeSVikram Kanigiri #include <debug.h> 10eb5e1be4SNariman Poushin #include <plat_arm.h> 11618f0feeSVikram Kanigiri #include <platform_def.h> 12618f0feeSVikram Kanigiri #include <tzc_dmc500.h> 13618f0feeSVikram Kanigiri 14618f0feeSVikram Kanigiri /******************************************************************************* 15618f0feeSVikram Kanigiri * Initialize the DMC500-TrustZone Controller for ARM standard platforms. 16618f0feeSVikram Kanigiri * When booting an EL3 payload, this is simplified: we configure region 0 with 17618f0feeSVikram Kanigiri * secure access only and do not enable any other region. 18618f0feeSVikram Kanigiri ******************************************************************************/ 1923411d2cSSummer Qin void arm_tzc_dmc500_setup(tzc_dmc500_driver_data_t *plat_driver_data, 2023411d2cSSummer Qin const arm_tzc_regions_info_t *tzc_regions) 21618f0feeSVikram Kanigiri { 2223411d2cSSummer Qin #ifndef EL3_PAYLOAD_BASE 23*af6491f8SAntonio Nino Diaz unsigned int region_index = 1U; 2423411d2cSSummer Qin const arm_tzc_regions_info_t *p; 2523411d2cSSummer Qin const arm_tzc_regions_info_t init_tzc_regions[] = { 2623411d2cSSummer Qin ARM_TZC_REGIONS_DEF, 2723411d2cSSummer Qin {0} 2823411d2cSSummer Qin }; 2923411d2cSSummer Qin #endif 3023411d2cSSummer Qin 31618f0feeSVikram Kanigiri assert(plat_driver_data); 32618f0feeSVikram Kanigiri 33618f0feeSVikram Kanigiri INFO("Configuring DMC-500 TZ Settings\n"); 34618f0feeSVikram Kanigiri 35618f0feeSVikram Kanigiri tzc_dmc500_driver_init(plat_driver_data); 36618f0feeSVikram Kanigiri 37618f0feeSVikram Kanigiri #ifndef EL3_PAYLOAD_BASE 3823411d2cSSummer Qin if (tzc_regions == NULL) 3923411d2cSSummer Qin p = init_tzc_regions; 4023411d2cSSummer Qin else 4123411d2cSSummer Qin p = tzc_regions; 4223411d2cSSummer Qin 43618f0feeSVikram Kanigiri /* Region 0 set to no access by default */ 44618f0feeSVikram Kanigiri tzc_dmc500_configure_region0(TZC_REGION_S_NONE, 0); 45618f0feeSVikram Kanigiri 4623411d2cSSummer Qin /* Rest Regions set according to tzc_regions array */ 4723411d2cSSummer Qin for (; p->base != 0ULL; p++) { 4823411d2cSSummer Qin tzc_dmc500_configure_region(region_index, p->base, p->end, 4923411d2cSSummer Qin p->sec_attr, p->nsaid_permissions); 5023411d2cSSummer Qin region_index++; 5123411d2cSSummer Qin } 52618f0feeSVikram Kanigiri 53*af6491f8SAntonio Nino Diaz INFO("Total %u regions set.\n", region_index); 54618f0feeSVikram Kanigiri 55618f0feeSVikram Kanigiri #else 56618f0feeSVikram Kanigiri /* Allow secure access only to DRAM for EL3 payloads */ 57618f0feeSVikram Kanigiri tzc_dmc500_configure_region0(TZC_REGION_S_RDWR, 0); 58618f0feeSVikram Kanigiri #endif 59618f0feeSVikram Kanigiri /* 60618f0feeSVikram Kanigiri * Raise an exception if a NS device tries to access secure memory 61618f0feeSVikram Kanigiri * TODO: Add interrupt handling support. 62618f0feeSVikram Kanigiri */ 63618f0feeSVikram Kanigiri tzc_dmc500_set_action(TZC_ACTION_RV_LOWERR); 64618f0feeSVikram Kanigiri 65618f0feeSVikram Kanigiri /* 66618f0feeSVikram Kanigiri * Flush the configuration settings to have an affect. Validate 67618f0feeSVikram Kanigiri * flush by checking FILTER_EN is set on region 1 attributes 68618f0feeSVikram Kanigiri * register. 69618f0feeSVikram Kanigiri */ 70618f0feeSVikram Kanigiri tzc_dmc500_config_complete(); 71618f0feeSVikram Kanigiri 72618f0feeSVikram Kanigiri /* 73618f0feeSVikram Kanigiri * Wait for the flush to complete. 74618f0feeSVikram Kanigiri * TODO: Have a timeout for this loop 75618f0feeSVikram Kanigiri */ 76618f0feeSVikram Kanigiri while (tzc_dmc500_verify_complete()) 77618f0feeSVikram Kanigiri ; 78618f0feeSVikram Kanigiri } 79