xref: /rk3399_ARM-atf/plat/arm/common/arm_tzc_dmc500.c (revision 82cb2c1ad9897473743f08437d0a3995bed561b9)
1618f0feeSVikram Kanigiri /*
2618f0feeSVikram Kanigiri  * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3618f0feeSVikram Kanigiri  *
4*82cb2c1aSdp-arm  * SPDX-License-Identifier: BSD-3-Clause
5618f0feeSVikram Kanigiri  */
6618f0feeSVikram Kanigiri 
7618f0feeSVikram Kanigiri #include <arm_def.h>
8618f0feeSVikram Kanigiri #include <assert.h>
9618f0feeSVikram Kanigiri #include <debug.h>
10618f0feeSVikram Kanigiri #include <platform_def.h>
11618f0feeSVikram Kanigiri #include <tzc_dmc500.h>
12618f0feeSVikram Kanigiri 
13618f0feeSVikram Kanigiri /*******************************************************************************
14618f0feeSVikram Kanigiri  * Initialize the DMC500-TrustZone Controller for ARM standard platforms.
15618f0feeSVikram Kanigiri  * Configure both the interfaces on Region 0 with no access, Region 1 with
16618f0feeSVikram Kanigiri  * secure access only, and the remaining DRAM regions access from the
17618f0feeSVikram Kanigiri  * given Non-Secure masters.
18618f0feeSVikram Kanigiri  *
19618f0feeSVikram Kanigiri  * When booting an EL3 payload, this is simplified: we configure region 0 with
20618f0feeSVikram Kanigiri  * secure access only and do not enable any other region.
21618f0feeSVikram Kanigiri  ******************************************************************************/
22618f0feeSVikram Kanigiri void arm_tzc_dmc500_setup(tzc_dmc500_driver_data_t *plat_driver_data)
23618f0feeSVikram Kanigiri {
24618f0feeSVikram Kanigiri 	assert(plat_driver_data);
25618f0feeSVikram Kanigiri 
26618f0feeSVikram Kanigiri 	INFO("Configuring DMC-500 TZ Settings\n");
27618f0feeSVikram Kanigiri 
28618f0feeSVikram Kanigiri 	tzc_dmc500_driver_init(plat_driver_data);
29618f0feeSVikram Kanigiri 
30618f0feeSVikram Kanigiri #ifndef EL3_PAYLOAD_BASE
31618f0feeSVikram Kanigiri 	/* Region 0 set to no access by default */
32618f0feeSVikram Kanigiri 	tzc_dmc500_configure_region0(TZC_REGION_S_NONE, 0);
33618f0feeSVikram Kanigiri 
34618f0feeSVikram Kanigiri 	/* Region 1 set to cover Secure part of DRAM */
35618f0feeSVikram Kanigiri 	tzc_dmc500_configure_region(1, ARM_AP_TZC_DRAM1_BASE,
36618f0feeSVikram Kanigiri 		ARM_AP_TZC_DRAM1_END,
37618f0feeSVikram Kanigiri 		TZC_REGION_S_RDWR,
38618f0feeSVikram Kanigiri 		0);
39618f0feeSVikram Kanigiri 
40618f0feeSVikram Kanigiri 	/* Region 2 set to cover Non-Secure access to 1st DRAM address range.*/
41618f0feeSVikram Kanigiri 	tzc_dmc500_configure_region(2,
42618f0feeSVikram Kanigiri 		ARM_NS_DRAM1_BASE,
43618f0feeSVikram Kanigiri 		ARM_NS_DRAM1_END,
44618f0feeSVikram Kanigiri 		TZC_REGION_S_NONE,
45618f0feeSVikram Kanigiri 		PLAT_ARM_TZC_NS_DEV_ACCESS);
46618f0feeSVikram Kanigiri 
47618f0feeSVikram Kanigiri 	/* Region 3 set to cover Non-Secure access to 2nd DRAM address range */
48618f0feeSVikram Kanigiri 	tzc_dmc500_configure_region(3,
49618f0feeSVikram Kanigiri 		ARM_DRAM2_BASE,
50618f0feeSVikram Kanigiri 		ARM_DRAM2_END,
51618f0feeSVikram Kanigiri 		TZC_REGION_S_NONE,
52618f0feeSVikram Kanigiri 		PLAT_ARM_TZC_NS_DEV_ACCESS);
53618f0feeSVikram Kanigiri #else
54618f0feeSVikram Kanigiri 	/* Allow secure access only to DRAM for EL3 payloads */
55618f0feeSVikram Kanigiri 	tzc_dmc500_configure_region0(TZC_REGION_S_RDWR, 0);
56618f0feeSVikram Kanigiri #endif
57618f0feeSVikram Kanigiri 	/*
58618f0feeSVikram Kanigiri 	 * Raise an exception if a NS device tries to access secure memory
59618f0feeSVikram Kanigiri 	 * TODO: Add interrupt handling support.
60618f0feeSVikram Kanigiri 	 */
61618f0feeSVikram Kanigiri 	tzc_dmc500_set_action(TZC_ACTION_RV_LOWERR);
62618f0feeSVikram Kanigiri 
63618f0feeSVikram Kanigiri 	/*
64618f0feeSVikram Kanigiri 	 * Flush the configuration settings to have an affect. Validate
65618f0feeSVikram Kanigiri 	 * flush by checking FILTER_EN is set on region 1 attributes
66618f0feeSVikram Kanigiri 	 * register.
67618f0feeSVikram Kanigiri 	 */
68618f0feeSVikram Kanigiri 	tzc_dmc500_config_complete();
69618f0feeSVikram Kanigiri 
70618f0feeSVikram Kanigiri 	/*
71618f0feeSVikram Kanigiri 	 * Wait for the flush to complete.
72618f0feeSVikram Kanigiri 	 * TODO: Have a timeout for this loop
73618f0feeSVikram Kanigiri 	 */
74618f0feeSVikram Kanigiri 	while (tzc_dmc500_verify_complete())
75618f0feeSVikram Kanigiri 		;
76618f0feeSVikram Kanigiri }
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