xref: /rk3399_ARM-atf/plat/arm/common/arm_tzc_dmc500.c (revision 23411d2c4adcec412befb4ffbbfbf81c743a59c6)
1618f0feeSVikram Kanigiri /*
2*23411d2cSSummer Qin  * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
3618f0feeSVikram Kanigiri  *
482cb2c1aSdp-arm  * SPDX-License-Identifier: BSD-3-Clause
5618f0feeSVikram Kanigiri  */
6618f0feeSVikram Kanigiri 
7618f0feeSVikram Kanigiri #include <arm_def.h>
8618f0feeSVikram Kanigiri #include <assert.h>
9618f0feeSVikram Kanigiri #include <debug.h>
10618f0feeSVikram Kanigiri #include <platform_def.h>
11618f0feeSVikram Kanigiri #include <tzc_dmc500.h>
12618f0feeSVikram Kanigiri 
13618f0feeSVikram Kanigiri /*******************************************************************************
14618f0feeSVikram Kanigiri  * Initialize the DMC500-TrustZone Controller for ARM standard platforms.
15618f0feeSVikram Kanigiri  * When booting an EL3 payload, this is simplified: we configure region 0 with
16618f0feeSVikram Kanigiri  * secure access only and do not enable any other region.
17618f0feeSVikram Kanigiri  ******************************************************************************/
18*23411d2cSSummer Qin void arm_tzc_dmc500_setup(tzc_dmc500_driver_data_t *plat_driver_data,
19*23411d2cSSummer Qin 			const arm_tzc_regions_info_t *tzc_regions)
20618f0feeSVikram Kanigiri {
21*23411d2cSSummer Qin #ifndef EL3_PAYLOAD_BASE
22*23411d2cSSummer Qin 	int region_index = 1;
23*23411d2cSSummer Qin 	const arm_tzc_regions_info_t *p;
24*23411d2cSSummer Qin 	const arm_tzc_regions_info_t init_tzc_regions[] = {
25*23411d2cSSummer Qin 		ARM_TZC_REGIONS_DEF,
26*23411d2cSSummer Qin 		{0}
27*23411d2cSSummer Qin 	};
28*23411d2cSSummer Qin #endif
29*23411d2cSSummer Qin 
30618f0feeSVikram Kanigiri 	assert(plat_driver_data);
31618f0feeSVikram Kanigiri 
32618f0feeSVikram Kanigiri 	INFO("Configuring DMC-500 TZ Settings\n");
33618f0feeSVikram Kanigiri 
34618f0feeSVikram Kanigiri 	tzc_dmc500_driver_init(plat_driver_data);
35618f0feeSVikram Kanigiri 
36618f0feeSVikram Kanigiri #ifndef EL3_PAYLOAD_BASE
37*23411d2cSSummer Qin 	if (tzc_regions == NULL)
38*23411d2cSSummer Qin 		p = init_tzc_regions;
39*23411d2cSSummer Qin 	else
40*23411d2cSSummer Qin 		p = tzc_regions;
41*23411d2cSSummer Qin 
42618f0feeSVikram Kanigiri 	/* Region 0 set to no access by default */
43618f0feeSVikram Kanigiri 	tzc_dmc500_configure_region0(TZC_REGION_S_NONE, 0);
44618f0feeSVikram Kanigiri 
45*23411d2cSSummer Qin 	/* Rest Regions set according to tzc_regions array */
46*23411d2cSSummer Qin 	for (; p->base != 0ULL; p++) {
47*23411d2cSSummer Qin 		tzc_dmc500_configure_region(region_index, p->base, p->end,
48*23411d2cSSummer Qin 					    p->sec_attr, p->nsaid_permissions);
49*23411d2cSSummer Qin 		region_index++;
50*23411d2cSSummer Qin 	}
51618f0feeSVikram Kanigiri 
52*23411d2cSSummer Qin 	INFO("Total %d regions set.\n", region_index);
53618f0feeSVikram Kanigiri 
54618f0feeSVikram Kanigiri #else
55618f0feeSVikram Kanigiri 	/* Allow secure access only to DRAM for EL3 payloads */
56618f0feeSVikram Kanigiri 	tzc_dmc500_configure_region0(TZC_REGION_S_RDWR, 0);
57618f0feeSVikram Kanigiri #endif
58618f0feeSVikram Kanigiri 	/*
59618f0feeSVikram Kanigiri 	 * Raise an exception if a NS device tries to access secure memory
60618f0feeSVikram Kanigiri 	 * TODO: Add interrupt handling support.
61618f0feeSVikram Kanigiri 	 */
62618f0feeSVikram Kanigiri 	tzc_dmc500_set_action(TZC_ACTION_RV_LOWERR);
63618f0feeSVikram Kanigiri 
64618f0feeSVikram Kanigiri 	/*
65618f0feeSVikram Kanigiri 	 * Flush the configuration settings to have an affect. Validate
66618f0feeSVikram Kanigiri 	 * flush by checking FILTER_EN is set on region 1 attributes
67618f0feeSVikram Kanigiri 	 * register.
68618f0feeSVikram Kanigiri 	 */
69618f0feeSVikram Kanigiri 	tzc_dmc500_config_complete();
70618f0feeSVikram Kanigiri 
71618f0feeSVikram Kanigiri 	/*
72618f0feeSVikram Kanigiri 	 * Wait for the flush to complete.
73618f0feeSVikram Kanigiri 	 * TODO: Have a timeout for this loop
74618f0feeSVikram Kanigiri 	 */
75618f0feeSVikram Kanigiri 	while (tzc_dmc500_verify_complete())
76618f0feeSVikram Kanigiri 		;
77618f0feeSVikram Kanigiri }
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