1a9cc84d7SVikram Kanigiri /* 21af540efSRoberto Vargas * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 3a9cc84d7SVikram Kanigiri * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5a9cc84d7SVikram Kanigiri */ 6a9cc84d7SVikram Kanigiri 709d40e0eSAntonio Nino Diaz #include <platform_def.h> 809d40e0eSAntonio Nino Diaz 909d40e0eSAntonio Nino Diaz #include <common/debug.h> 1009d40e0eSAntonio Nino Diaz #include <drivers/arm/tzc400.h> 11*bd9344f6SAntonio Nino Diaz #include <plat/arm/common/plat_arm.h> 12a9cc84d7SVikram Kanigiri 13a9cc84d7SVikram Kanigiri /* Weak definitions may be overridden in specific ARM standard platform */ 14a9cc84d7SVikram Kanigiri #pragma weak plat_arm_security_setup 15a9cc84d7SVikram Kanigiri 16a9cc84d7SVikram Kanigiri 17a9cc84d7SVikram Kanigiri /******************************************************************************* 18a9cc84d7SVikram Kanigiri * Initialize the TrustZone Controller for ARM standard platforms. 19a9cc84d7SVikram Kanigiri * When booting an EL3 payload, this is simplified: we configure region 0 with 20a9cc84d7SVikram Kanigiri * secure access only and do not enable any other region. 21a9cc84d7SVikram Kanigiri ******************************************************************************/ 2223411d2cSSummer Qin void arm_tzc400_setup(const arm_tzc_regions_info_t *tzc_regions) 23a9cc84d7SVikram Kanigiri { 2423411d2cSSummer Qin #ifndef EL3_PAYLOAD_BASE 25af6491f8SAntonio Nino Diaz unsigned int region_index = 1U; 2623411d2cSSummer Qin const arm_tzc_regions_info_t *p; 2723411d2cSSummer Qin const arm_tzc_regions_info_t init_tzc_regions[] = { 2823411d2cSSummer Qin ARM_TZC_REGIONS_DEF, 2923411d2cSSummer Qin {0} 3023411d2cSSummer Qin }; 3123411d2cSSummer Qin #endif 3223411d2cSSummer Qin 33a9cc84d7SVikram Kanigiri INFO("Configuring TrustZone Controller\n"); 34a9cc84d7SVikram Kanigiri 3557f78201SSoby Mathew tzc400_init(PLAT_ARM_TZC_BASE); 36a9cc84d7SVikram Kanigiri 37a9cc84d7SVikram Kanigiri /* Disable filters. */ 3857f78201SSoby Mathew tzc400_disable_filters(); 39a9cc84d7SVikram Kanigiri 40a9cc84d7SVikram Kanigiri #ifndef EL3_PAYLOAD_BASE 4123411d2cSSummer Qin if (tzc_regions == NULL) 4223411d2cSSummer Qin p = init_tzc_regions; 4323411d2cSSummer Qin else 4423411d2cSSummer Qin p = tzc_regions; 45e60f2af9SSoby Mathew 46a9cc84d7SVikram Kanigiri /* Region 0 set to no access by default */ 4757f78201SSoby Mathew tzc400_configure_region0(TZC_REGION_S_NONE, 0); 48a9cc84d7SVikram Kanigiri 4923411d2cSSummer Qin /* Rest Regions set according to tzc_regions array */ 5023411d2cSSummer Qin for (; p->base != 0ULL; p++) { 5123411d2cSSummer Qin tzc400_configure_region(PLAT_ARM_TZC_FILTERS, region_index, 5223411d2cSSummer Qin p->base, p->end, p->sec_attr, p->nsaid_permissions); 5323411d2cSSummer Qin region_index++; 5423411d2cSSummer Qin } 55a9cc84d7SVikram Kanigiri 56af6491f8SAntonio Nino Diaz INFO("Total %u regions set.\n", region_index); 57e29efeb1SAntonio Nino Diaz 58e29efeb1SAntonio Nino Diaz #else /* if defined(EL3_PAYLOAD_BASE) */ 59e29efeb1SAntonio Nino Diaz 60fb48b970SSoby Mathew /* Allow Secure and Non-secure access to DRAM for EL3 payloads */ 61fb48b970SSoby Mathew tzc400_configure_region0(TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS); 62e29efeb1SAntonio Nino Diaz 63a9cc84d7SVikram Kanigiri #endif /* EL3_PAYLOAD_BASE */ 64a9cc84d7SVikram Kanigiri 65a9cc84d7SVikram Kanigiri /* 66a9cc84d7SVikram Kanigiri * Raise an exception if a NS device tries to access secure memory 67a9cc84d7SVikram Kanigiri * TODO: Add interrupt handling support. 68a9cc84d7SVikram Kanigiri */ 6957f78201SSoby Mathew tzc400_set_action(TZC_ACTION_ERR); 70a9cc84d7SVikram Kanigiri 71a9cc84d7SVikram Kanigiri /* Enable filters. */ 7257f78201SSoby Mathew tzc400_enable_filters(); 73a9cc84d7SVikram Kanigiri } 74a9cc84d7SVikram Kanigiri 75a9cc84d7SVikram Kanigiri void plat_arm_security_setup(void) 76a9cc84d7SVikram Kanigiri { 7723411d2cSSummer Qin arm_tzc400_setup(NULL); 78a9cc84d7SVikram Kanigiri } 79