1a9cc84d7SVikram Kanigiri /* 21af540efSRoberto Vargas * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 3a9cc84d7SVikram Kanigiri * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5a9cc84d7SVikram Kanigiri */ 6a9cc84d7SVikram Kanigiri 7*09d40e0eSAntonio Nino Diaz #include <platform_def.h> 8*09d40e0eSAntonio Nino Diaz 9*09d40e0eSAntonio Nino Diaz #include <common/debug.h> 10*09d40e0eSAntonio Nino Diaz #include <drivers/arm/tzc400.h> 11*09d40e0eSAntonio Nino Diaz 12a9cc84d7SVikram Kanigiri #include <arm_def.h> 13e29efeb1SAntonio Nino Diaz #include <arm_spm_def.h> 141af540efSRoberto Vargas #include <plat_arm.h> 15a9cc84d7SVikram Kanigiri 16a9cc84d7SVikram Kanigiri /* Weak definitions may be overridden in specific ARM standard platform */ 17a9cc84d7SVikram Kanigiri #pragma weak plat_arm_security_setup 18a9cc84d7SVikram Kanigiri 19a9cc84d7SVikram Kanigiri 20a9cc84d7SVikram Kanigiri /******************************************************************************* 21a9cc84d7SVikram Kanigiri * Initialize the TrustZone Controller for ARM standard platforms. 22a9cc84d7SVikram Kanigiri * When booting an EL3 payload, this is simplified: we configure region 0 with 23a9cc84d7SVikram Kanigiri * secure access only and do not enable any other region. 24a9cc84d7SVikram Kanigiri ******************************************************************************/ 2523411d2cSSummer Qin void arm_tzc400_setup(const arm_tzc_regions_info_t *tzc_regions) 26a9cc84d7SVikram Kanigiri { 2723411d2cSSummer Qin #ifndef EL3_PAYLOAD_BASE 28af6491f8SAntonio Nino Diaz unsigned int region_index = 1U; 2923411d2cSSummer Qin const arm_tzc_regions_info_t *p; 3023411d2cSSummer Qin const arm_tzc_regions_info_t init_tzc_regions[] = { 3123411d2cSSummer Qin ARM_TZC_REGIONS_DEF, 3223411d2cSSummer Qin {0} 3323411d2cSSummer Qin }; 3423411d2cSSummer Qin #endif 3523411d2cSSummer Qin 36a9cc84d7SVikram Kanigiri INFO("Configuring TrustZone Controller\n"); 37a9cc84d7SVikram Kanigiri 3857f78201SSoby Mathew tzc400_init(PLAT_ARM_TZC_BASE); 39a9cc84d7SVikram Kanigiri 40a9cc84d7SVikram Kanigiri /* Disable filters. */ 4157f78201SSoby Mathew tzc400_disable_filters(); 42a9cc84d7SVikram Kanigiri 43a9cc84d7SVikram Kanigiri #ifndef EL3_PAYLOAD_BASE 4423411d2cSSummer Qin if (tzc_regions == NULL) 4523411d2cSSummer Qin p = init_tzc_regions; 4623411d2cSSummer Qin else 4723411d2cSSummer Qin p = tzc_regions; 48e60f2af9SSoby Mathew 49a9cc84d7SVikram Kanigiri /* Region 0 set to no access by default */ 5057f78201SSoby Mathew tzc400_configure_region0(TZC_REGION_S_NONE, 0); 51a9cc84d7SVikram Kanigiri 5223411d2cSSummer Qin /* Rest Regions set according to tzc_regions array */ 5323411d2cSSummer Qin for (; p->base != 0ULL; p++) { 5423411d2cSSummer Qin tzc400_configure_region(PLAT_ARM_TZC_FILTERS, region_index, 5523411d2cSSummer Qin p->base, p->end, p->sec_attr, p->nsaid_permissions); 5623411d2cSSummer Qin region_index++; 5723411d2cSSummer Qin } 58a9cc84d7SVikram Kanigiri 59af6491f8SAntonio Nino Diaz INFO("Total %u regions set.\n", region_index); 60e29efeb1SAntonio Nino Diaz 61e29efeb1SAntonio Nino Diaz #else /* if defined(EL3_PAYLOAD_BASE) */ 62e29efeb1SAntonio Nino Diaz 63fb48b970SSoby Mathew /* Allow Secure and Non-secure access to DRAM for EL3 payloads */ 64fb48b970SSoby Mathew tzc400_configure_region0(TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS); 65e29efeb1SAntonio Nino Diaz 66a9cc84d7SVikram Kanigiri #endif /* EL3_PAYLOAD_BASE */ 67a9cc84d7SVikram Kanigiri 68a9cc84d7SVikram Kanigiri /* 69a9cc84d7SVikram Kanigiri * Raise an exception if a NS device tries to access secure memory 70a9cc84d7SVikram Kanigiri * TODO: Add interrupt handling support. 71a9cc84d7SVikram Kanigiri */ 7257f78201SSoby Mathew tzc400_set_action(TZC_ACTION_ERR); 73a9cc84d7SVikram Kanigiri 74a9cc84d7SVikram Kanigiri /* Enable filters. */ 7557f78201SSoby Mathew tzc400_enable_filters(); 76a9cc84d7SVikram Kanigiri } 77a9cc84d7SVikram Kanigiri 78a9cc84d7SVikram Kanigiri void plat_arm_security_setup(void) 79a9cc84d7SVikram Kanigiri { 8023411d2cSSummer Qin arm_tzc400_setup(NULL); 81a9cc84d7SVikram Kanigiri } 82