1b4315306SDan Handley /* 2*d8d6cf24SSummer Qin * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3b4315306SDan Handley * 4b4315306SDan Handley * Redistribution and use in source and binary forms, with or without 5b4315306SDan Handley * modification, are permitted provided that the following conditions are met: 6b4315306SDan Handley * 7b4315306SDan Handley * Redistributions of source code must retain the above copyright notice, this 8b4315306SDan Handley * list of conditions and the following disclaimer. 9b4315306SDan Handley * 10b4315306SDan Handley * Redistributions in binary form must reproduce the above copyright notice, 11b4315306SDan Handley * this list of conditions and the following disclaimer in the documentation 12b4315306SDan Handley * and/or other materials provided with the distribution. 13b4315306SDan Handley * 14b4315306SDan Handley * Neither the name of ARM nor the names of its contributors may be used 15b4315306SDan Handley * to endorse or promote products derived from this software without specific 16b4315306SDan Handley * prior written permission. 17b4315306SDan Handley * 18b4315306SDan Handley * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19b4315306SDan Handley * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20b4315306SDan Handley * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21b4315306SDan Handley * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22b4315306SDan Handley * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23b4315306SDan Handley * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24b4315306SDan Handley * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25b4315306SDan Handley * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26b4315306SDan Handley * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27b4315306SDan Handley * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28b4315306SDan Handley * POSSIBILITY OF SUCH DAMAGE. 29b4315306SDan Handley */ 30b4315306SDan Handley 31b4315306SDan Handley #include <arch.h> 3238dce70fSSoby Mathew #include <plat_arm.h> 33b4315306SDan Handley #include <platform_def.h> 34b4315306SDan Handley 3538dce70fSSoby Mathew /******************************************************************************* 3638dce70fSSoby Mathew * This function validates an MPIDR by checking whether it falls within the 3738dce70fSSoby Mathew * acceptable bounds. An error code (-1) is returned if an incorrect mpidr 3838dce70fSSoby Mathew * is passed. 3938dce70fSSoby Mathew ******************************************************************************/ 4038dce70fSSoby Mathew int arm_check_mpidr(u_register_t mpidr) 41b4315306SDan Handley { 4238dce70fSSoby Mathew unsigned int cluster_id, cpu_id; 43*d8d6cf24SSummer Qin uint64_t valid_mask; 44b4315306SDan Handley 45*d8d6cf24SSummer Qin #if ARM_PLAT_MT 46*d8d6cf24SSummer Qin unsigned int pe_id; 4738dce70fSSoby Mathew 48*d8d6cf24SSummer Qin valid_mask = ~(MPIDR_AFFLVL_MASK | 49*d8d6cf24SSummer Qin (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | 50*d8d6cf24SSummer Qin (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)); 51*d8d6cf24SSummer Qin cluster_id = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK; 52*d8d6cf24SSummer Qin cpu_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; 53*d8d6cf24SSummer Qin pe_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; 54*d8d6cf24SSummer Qin #else 55*d8d6cf24SSummer Qin valid_mask = ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK); 5638dce70fSSoby Mathew cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; 5738dce70fSSoby Mathew cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; 58*d8d6cf24SSummer Qin #endif /* ARM_PLAT_MT */ 59*d8d6cf24SSummer Qin 60*d8d6cf24SSummer Qin mpidr &= MPIDR_AFFINITY_MASK; 61*d8d6cf24SSummer Qin if (mpidr & valid_mask) 62*d8d6cf24SSummer Qin return -1; 6338dce70fSSoby Mathew 640108047aSSoby Mathew if (cluster_id >= PLAT_ARM_CLUSTER_COUNT) 6538dce70fSSoby Mathew return -1; 6638dce70fSSoby Mathew 6738dce70fSSoby Mathew /* Validate cpu_id by checking whether it represents a CPU in 6838dce70fSSoby Mathew one of the two clusters present on the platform. */ 690108047aSSoby Mathew if (cpu_id >= plat_arm_get_cluster_core_count(mpidr)) 7038dce70fSSoby Mathew return -1; 7138dce70fSSoby Mathew 72*d8d6cf24SSummer Qin #if ARM_PLAT_MT 73*d8d6cf24SSummer Qin if (pe_id >= plat_arm_get_cpu_pe_count(mpidr)) 74*d8d6cf24SSummer Qin return -1; 75*d8d6cf24SSummer Qin #endif /* ARM_PLAT_MT */ 76*d8d6cf24SSummer Qin 7738dce70fSSoby Mathew return 0; 78b4315306SDan Handley } 79