1b4315306SDan Handley /* 2d8d6cf24SSummer Qin * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3b4315306SDan Handley * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5b4315306SDan Handley */ 6b4315306SDan Handley 7b4315306SDan Handley #include <platform_def.h> 8b4315306SDan Handley 909d40e0eSAntonio Nino Diaz #include <arch.h> 10*bd9344f6SAntonio Nino Diaz #include <plat/arm/common/plat_arm.h> 1109d40e0eSAntonio Nino Diaz 1238dce70fSSoby Mathew /******************************************************************************* 1338dce70fSSoby Mathew * This function validates an MPIDR by checking whether it falls within the 1438dce70fSSoby Mathew * acceptable bounds. An error code (-1) is returned if an incorrect mpidr 1538dce70fSSoby Mathew * is passed. 1638dce70fSSoby Mathew ******************************************************************************/ 1738dce70fSSoby Mathew int arm_check_mpidr(u_register_t mpidr) 18b4315306SDan Handley { 1938dce70fSSoby Mathew unsigned int cluster_id, cpu_id; 20d8d6cf24SSummer Qin uint64_t valid_mask; 21b4315306SDan Handley 22d8d6cf24SSummer Qin #if ARM_PLAT_MT 23d8d6cf24SSummer Qin unsigned int pe_id; 2438dce70fSSoby Mathew 25d8d6cf24SSummer Qin valid_mask = ~(MPIDR_AFFLVL_MASK | 26d8d6cf24SSummer Qin (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | 27d8d6cf24SSummer Qin (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)); 28d8d6cf24SSummer Qin cluster_id = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK; 29d8d6cf24SSummer Qin cpu_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; 30d8d6cf24SSummer Qin pe_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; 31d8d6cf24SSummer Qin #else 32d8d6cf24SSummer Qin valid_mask = ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK); 3389509904SSathees Balya cluster_id = (unsigned int) ((mpidr >> MPIDR_AFF1_SHIFT) & 3489509904SSathees Balya MPIDR_AFFLVL_MASK); 3589509904SSathees Balya cpu_id = (unsigned int) ((mpidr >> MPIDR_AFF0_SHIFT) & 3689509904SSathees Balya MPIDR_AFFLVL_MASK); 37d8d6cf24SSummer Qin #endif /* ARM_PLAT_MT */ 38d8d6cf24SSummer Qin 39d8d6cf24SSummer Qin mpidr &= MPIDR_AFFINITY_MASK; 4089509904SSathees Balya if ((mpidr & valid_mask) != 0U) 41d8d6cf24SSummer Qin return -1; 4238dce70fSSoby Mathew 430108047aSSoby Mathew if (cluster_id >= PLAT_ARM_CLUSTER_COUNT) 4438dce70fSSoby Mathew return -1; 4538dce70fSSoby Mathew 4638dce70fSSoby Mathew /* Validate cpu_id by checking whether it represents a CPU in 4738dce70fSSoby Mathew one of the two clusters present on the platform. */ 480108047aSSoby Mathew if (cpu_id >= plat_arm_get_cluster_core_count(mpidr)) 4938dce70fSSoby Mathew return -1; 5038dce70fSSoby Mathew 51d8d6cf24SSummer Qin #if ARM_PLAT_MT 52d8d6cf24SSummer Qin if (pe_id >= plat_arm_get_cpu_pe_count(mpidr)) 53d8d6cf24SSummer Qin return -1; 54d8d6cf24SSummer Qin #endif /* ARM_PLAT_MT */ 55d8d6cf24SSummer Qin 5638dce70fSSoby Mathew return 0; 57b4315306SDan Handley } 58