1b4315306SDan Handley /* 2d8d6cf24SSummer Qin * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3b4315306SDan Handley * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5b4315306SDan Handley */ 6b4315306SDan Handley 7b4315306SDan Handley #include <arch.h> 838dce70fSSoby Mathew #include <plat_arm.h> 9b4315306SDan Handley #include <platform_def.h> 10b4315306SDan Handley 1138dce70fSSoby Mathew /******************************************************************************* 1238dce70fSSoby Mathew * This function validates an MPIDR by checking whether it falls within the 1338dce70fSSoby Mathew * acceptable bounds. An error code (-1) is returned if an incorrect mpidr 1438dce70fSSoby Mathew * is passed. 1538dce70fSSoby Mathew ******************************************************************************/ 1638dce70fSSoby Mathew int arm_check_mpidr(u_register_t mpidr) 17b4315306SDan Handley { 1838dce70fSSoby Mathew unsigned int cluster_id, cpu_id; 19d8d6cf24SSummer Qin uint64_t valid_mask; 20b4315306SDan Handley 21d8d6cf24SSummer Qin #if ARM_PLAT_MT 22d8d6cf24SSummer Qin unsigned int pe_id; 2338dce70fSSoby Mathew 24d8d6cf24SSummer Qin valid_mask = ~(MPIDR_AFFLVL_MASK | 25d8d6cf24SSummer Qin (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | 26d8d6cf24SSummer Qin (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)); 27d8d6cf24SSummer Qin cluster_id = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK; 28d8d6cf24SSummer Qin cpu_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; 29d8d6cf24SSummer Qin pe_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; 30d8d6cf24SSummer Qin #else 31d8d6cf24SSummer Qin valid_mask = ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK); 3238dce70fSSoby Mathew cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; 3338dce70fSSoby Mathew cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; 34d8d6cf24SSummer Qin #endif /* ARM_PLAT_MT */ 35d8d6cf24SSummer Qin 36d8d6cf24SSummer Qin mpidr &= MPIDR_AFFINITY_MASK; 37d8d6cf24SSummer Qin if (mpidr & valid_mask) 38d8d6cf24SSummer Qin return -1; 3938dce70fSSoby Mathew 400108047aSSoby Mathew if (cluster_id >= PLAT_ARM_CLUSTER_COUNT) 4138dce70fSSoby Mathew return -1; 4238dce70fSSoby Mathew 4338dce70fSSoby Mathew /* Validate cpu_id by checking whether it represents a CPU in 4438dce70fSSoby Mathew one of the two clusters present on the platform. */ 450108047aSSoby Mathew if (cpu_id >= plat_arm_get_cluster_core_count(mpidr)) 4638dce70fSSoby Mathew return -1; 4738dce70fSSoby Mathew 48d8d6cf24SSummer Qin #if ARM_PLAT_MT 49d8d6cf24SSummer Qin if (pe_id >= plat_arm_get_cpu_pe_count(mpidr)) 50d8d6cf24SSummer Qin return -1; 51d8d6cf24SSummer Qin #endif /* ARM_PLAT_MT */ 52d8d6cf24SSummer Qin 5338dce70fSSoby Mathew return 0; 54b4315306SDan Handley } 55