1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <arm_def.h> 9 #include <arm_gic.h> 10 #include <assert.h> 11 #include <errno.h> 12 #include <plat_arm.h> 13 #include <platform.h> 14 #include <platform_def.h> 15 #include <psci.h> 16 17 /* Allow ARM Standard platforms to override this function */ 18 #pragma weak plat_arm_psci_override_pm_ops 19 20 #if ARM_RECOM_STATE_ID_ENC 21 extern unsigned int arm_pm_idle_states[]; 22 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 23 24 #if !ARM_RECOM_STATE_ID_ENC 25 /******************************************************************************* 26 * ARM standard platform handler called to check the validity of the power state 27 * parameter. 28 ******************************************************************************/ 29 int arm_validate_power_state(unsigned int power_state, 30 psci_power_state_t *req_state) 31 { 32 int pstate = psci_get_pstate_type(power_state); 33 int pwr_lvl = psci_get_pstate_pwrlvl(power_state); 34 int i; 35 36 assert(req_state); 37 38 if (pwr_lvl > PLAT_MAX_PWR_LVL) 39 return PSCI_E_INVALID_PARAMS; 40 41 /* Sanity check the requested state */ 42 if (pstate == PSTATE_TYPE_STANDBY) { 43 /* 44 * It's possible to enter standby only on power level 0 45 * Ignore any other power level. 46 */ 47 if (pwr_lvl != ARM_PWR_LVL0) 48 return PSCI_E_INVALID_PARAMS; 49 50 req_state->pwr_domain_state[ARM_PWR_LVL0] = 51 ARM_LOCAL_STATE_RET; 52 } else { 53 for (i = ARM_PWR_LVL0; i <= pwr_lvl; i++) 54 req_state->pwr_domain_state[i] = 55 ARM_LOCAL_STATE_OFF; 56 } 57 58 /* 59 * We expect the 'state id' to be zero. 60 */ 61 if (psci_get_pstate_id(power_state)) 62 return PSCI_E_INVALID_PARAMS; 63 64 return PSCI_E_SUCCESS; 65 } 66 67 #else 68 /******************************************************************************* 69 * ARM standard platform handler called to check the validity of the power 70 * state parameter. The power state parameter has to be a composite power 71 * state. 72 ******************************************************************************/ 73 int arm_validate_power_state(unsigned int power_state, 74 psci_power_state_t *req_state) 75 { 76 unsigned int state_id; 77 int i; 78 79 assert(req_state); 80 81 /* 82 * Currently we are using a linear search for finding the matching 83 * entry in the idle power state array. This can be made a binary 84 * search if the number of entries justify the additional complexity. 85 */ 86 for (i = 0; !!arm_pm_idle_states[i]; i++) { 87 if (power_state == arm_pm_idle_states[i]) 88 break; 89 } 90 91 /* Return error if entry not found in the idle state array */ 92 if (!arm_pm_idle_states[i]) 93 return PSCI_E_INVALID_PARAMS; 94 95 i = 0; 96 state_id = psci_get_pstate_id(power_state); 97 98 /* Parse the State ID and populate the state info parameter */ 99 while (state_id) { 100 req_state->pwr_domain_state[i++] = state_id & 101 ARM_LOCAL_PSTATE_MASK; 102 state_id >>= ARM_LOCAL_PSTATE_WIDTH; 103 } 104 105 return PSCI_E_SUCCESS; 106 } 107 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 108 109 /******************************************************************************* 110 * ARM standard platform handler called to check the validity of the non secure 111 * entrypoint. Returns 0 if the entrypoint is valid, or -1 otherwise. 112 ******************************************************************************/ 113 int arm_validate_ns_entrypoint(uintptr_t entrypoint) 114 { 115 /* 116 * Check if the non secure entrypoint lies within the non 117 * secure DRAM. 118 */ 119 if ((entrypoint >= ARM_NS_DRAM1_BASE) && (entrypoint < 120 (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) { 121 return 0; 122 } 123 #ifndef AARCH32 124 if ((entrypoint >= ARM_DRAM2_BASE) && (entrypoint < 125 (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) { 126 return 0; 127 } 128 #endif 129 130 return -1; 131 } 132 133 int arm_validate_psci_entrypoint(uintptr_t entrypoint) 134 { 135 return arm_validate_ns_entrypoint(entrypoint) == 0 ? PSCI_E_SUCCESS : 136 PSCI_E_INVALID_ADDRESS; 137 } 138 139 /****************************************************************************** 140 * Default definition on ARM standard platforms to override the plat_psci_ops. 141 *****************************************************************************/ 142 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) 143 { 144 return ops; 145 } 146 147 /****************************************************************************** 148 * Helper function to save the platform state before a system suspend. Save the 149 * state of the system components which are not in the Always ON power domain. 150 *****************************************************************************/ 151 void arm_system_pwr_domain_save(void) 152 { 153 /* Assert system power domain is available on the platform */ 154 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); 155 156 plat_arm_gic_save(); 157 158 /* 159 * Unregister console now so that it is not registered for a second 160 * time during resume. 161 */ 162 arm_console_runtime_end(); 163 164 /* 165 * All the other peripheral which are configured by ARM TF are 166 * re-initialized on resume from system suspend. Hence we 167 * don't save their state here. 168 */ 169 } 170 171 /****************************************************************************** 172 * Helper function to resume the platform from system suspend. Reinitialize 173 * the system components which are not in the Always ON power domain. 174 * TODO: Unify the platform setup when waking up from cold boot and system 175 * resume in arm_bl31_platform_setup(). 176 *****************************************************************************/ 177 void arm_system_pwr_domain_resume(void) 178 { 179 /* Initialize the console */ 180 arm_console_runtime_init(); 181 182 /* Assert system power domain is available on the platform */ 183 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); 184 185 plat_arm_gic_resume(); 186 187 plat_arm_security_setup(); 188 arm_configure_sys_timer(); 189 } 190 191 /******************************************************************************* 192 * Private function to program the mailbox for a cpu before it is released 193 * from reset. This function assumes that the Trusted mail box base is within 194 * the ARM_SHARED_RAM region 195 ******************************************************************************/ 196 void arm_program_trusted_mailbox(uintptr_t address) 197 { 198 uintptr_t *mailbox = (void *) PLAT_ARM_TRUSTED_MAILBOX_BASE; 199 200 *mailbox = address; 201 202 /* 203 * Ensure that the PLAT_ARM_TRUSTED_MAILBOX_BASE is within 204 * ARM_SHARED_RAM region. 205 */ 206 assert((PLAT_ARM_TRUSTED_MAILBOX_BASE >= ARM_SHARED_RAM_BASE) && 207 ((PLAT_ARM_TRUSTED_MAILBOX_BASE + sizeof(*mailbox)) <= \ 208 (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE))); 209 } 210 211 /******************************************************************************* 212 * The ARM Standard platform definition of platform porting API 213 * `plat_setup_psci_ops`. 214 ******************************************************************************/ 215 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 216 const plat_psci_ops_t **psci_ops) 217 { 218 *psci_ops = plat_arm_psci_override_pm_ops(&plat_arm_psci_pm_ops); 219 220 /* Setup mailbox with entry point. */ 221 arm_program_trusted_mailbox(sec_entrypoint); 222 return 0; 223 } 224