1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <arm_def.h> 9 #include <arm_gic.h> 10 #include <assert.h> 11 #include <errno.h> 12 #include <plat_arm.h> 13 #include <platform.h> 14 #include <platform_def.h> 15 #include <psci.h> 16 17 /* Allow ARM Standard platforms to override these functions */ 18 #pragma weak plat_arm_psci_override_pm_ops 19 #pragma weak plat_arm_program_trusted_mailbox 20 21 #if !ARM_RECOM_STATE_ID_ENC 22 /******************************************************************************* 23 * ARM standard platform handler called to check the validity of the power state 24 * parameter. 25 ******************************************************************************/ 26 int arm_validate_power_state(unsigned int power_state, 27 psci_power_state_t *req_state) 28 { 29 unsigned int pstate = psci_get_pstate_type(power_state); 30 unsigned int pwr_lvl = psci_get_pstate_pwrlvl(power_state); 31 unsigned int i; 32 33 assert(req_state > 0U); 34 35 if (pwr_lvl > PLAT_MAX_PWR_LVL) 36 return PSCI_E_INVALID_PARAMS; 37 38 /* Sanity check the requested state */ 39 if (pstate == PSTATE_TYPE_STANDBY) { 40 /* 41 * It's possible to enter standby only on power level 0 42 * Ignore any other power level. 43 */ 44 if (pwr_lvl != ARM_PWR_LVL0) 45 return PSCI_E_INVALID_PARAMS; 46 47 req_state->pwr_domain_state[ARM_PWR_LVL0] = 48 ARM_LOCAL_STATE_RET; 49 } else { 50 for (i = ARM_PWR_LVL0; i <= pwr_lvl; i++) 51 req_state->pwr_domain_state[i] = 52 ARM_LOCAL_STATE_OFF; 53 } 54 55 /* 56 * We expect the 'state id' to be zero. 57 */ 58 if (psci_get_pstate_id(power_state) != 0U) 59 return PSCI_E_INVALID_PARAMS; 60 61 return PSCI_E_SUCCESS; 62 } 63 64 #else 65 /******************************************************************************* 66 * ARM standard platform handler called to check the validity of the power 67 * state parameter. The power state parameter has to be a composite power 68 * state. 69 ******************************************************************************/ 70 int arm_validate_power_state(unsigned int power_state, 71 psci_power_state_t *req_state) 72 { 73 unsigned int state_id; 74 int i; 75 76 assert(req_state); 77 78 /* 79 * Currently we are using a linear search for finding the matching 80 * entry in the idle power state array. This can be made a binary 81 * search if the number of entries justify the additional complexity. 82 */ 83 for (i = 0; !!arm_pm_idle_states[i]; i++) { 84 if (power_state == arm_pm_idle_states[i]) 85 break; 86 } 87 88 /* Return error if entry not found in the idle state array */ 89 if (!arm_pm_idle_states[i]) 90 return PSCI_E_INVALID_PARAMS; 91 92 i = 0; 93 state_id = psci_get_pstate_id(power_state); 94 95 /* Parse the State ID and populate the state info parameter */ 96 while (state_id) { 97 req_state->pwr_domain_state[i++] = state_id & 98 ARM_LOCAL_PSTATE_MASK; 99 state_id >>= ARM_LOCAL_PSTATE_WIDTH; 100 } 101 102 return PSCI_E_SUCCESS; 103 } 104 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 105 106 /******************************************************************************* 107 * ARM standard platform handler called to check the validity of the non secure 108 * entrypoint. Returns 0 if the entrypoint is valid, or -1 otherwise. 109 ******************************************************************************/ 110 int arm_validate_ns_entrypoint(uintptr_t entrypoint) 111 { 112 /* 113 * Check if the non secure entrypoint lies within the non 114 * secure DRAM. 115 */ 116 if ((entrypoint >= ARM_NS_DRAM1_BASE) && (entrypoint < 117 (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) { 118 return 0; 119 } 120 #ifndef AARCH32 121 if ((entrypoint >= ARM_DRAM2_BASE) && (entrypoint < 122 (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) { 123 return 0; 124 } 125 #endif 126 127 return -1; 128 } 129 130 int arm_validate_psci_entrypoint(uintptr_t entrypoint) 131 { 132 return arm_validate_ns_entrypoint(entrypoint) == 0 ? PSCI_E_SUCCESS : 133 PSCI_E_INVALID_ADDRESS; 134 } 135 136 /****************************************************************************** 137 * Default definition on ARM standard platforms to override the plat_psci_ops. 138 *****************************************************************************/ 139 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) 140 { 141 return ops; 142 } 143 144 /****************************************************************************** 145 * Helper function to save the platform state before a system suspend. Save the 146 * state of the system components which are not in the Always ON power domain. 147 *****************************************************************************/ 148 void arm_system_pwr_domain_save(void) 149 { 150 /* Assert system power domain is available on the platform */ 151 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); 152 153 plat_arm_gic_save(); 154 155 /* 156 * Unregister console now so that it is not registered for a second 157 * time during resume. 158 */ 159 arm_console_runtime_end(); 160 161 /* 162 * All the other peripheral which are configured by ARM TF are 163 * re-initialized on resume from system suspend. Hence we 164 * don't save their state here. 165 */ 166 } 167 168 /****************************************************************************** 169 * Helper function to resume the platform from system suspend. Reinitialize 170 * the system components which are not in the Always ON power domain. 171 * TODO: Unify the platform setup when waking up from cold boot and system 172 * resume in arm_bl31_platform_setup(). 173 *****************************************************************************/ 174 void arm_system_pwr_domain_resume(void) 175 { 176 /* Initialize the console */ 177 arm_console_runtime_init(); 178 179 /* Assert system power domain is available on the platform */ 180 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); 181 182 plat_arm_gic_resume(); 183 184 plat_arm_security_setup(); 185 arm_configure_sys_timer(); 186 } 187 188 /******************************************************************************* 189 * ARM platform function to program the mailbox for a cpu before it is released 190 * from reset. This function assumes that the Trusted mail box base is within 191 * the ARM_SHARED_RAM region 192 ******************************************************************************/ 193 void plat_arm_program_trusted_mailbox(uintptr_t address) 194 { 195 uintptr_t *mailbox = (void *) PLAT_ARM_TRUSTED_MAILBOX_BASE; 196 197 *mailbox = address; 198 199 /* 200 * Ensure that the PLAT_ARM_TRUSTED_MAILBOX_BASE is within 201 * ARM_SHARED_RAM region. 202 */ 203 assert((PLAT_ARM_TRUSTED_MAILBOX_BASE >= ARM_SHARED_RAM_BASE) && 204 ((PLAT_ARM_TRUSTED_MAILBOX_BASE + sizeof(*mailbox)) <= \ 205 (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE))); 206 } 207 208 /******************************************************************************* 209 * The ARM Standard platform definition of platform porting API 210 * `plat_setup_psci_ops`. 211 ******************************************************************************/ 212 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 213 const plat_psci_ops_t **psci_ops) 214 { 215 *psci_ops = plat_arm_psci_override_pm_ops(&plat_arm_psci_pm_ops); 216 217 /* Setup mailbox with entry point. */ 218 plat_arm_program_trusted_mailbox(sec_entrypoint); 219 return 0; 220 } 221