1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <arm_def.h> 9 #include <assert.h> 10 #include <errno.h> 11 #include <plat_arm.h> 12 #include <platform.h> 13 #include <platform_def.h> 14 #include <psci.h> 15 16 /* Allow ARM Standard platforms to override these functions */ 17 #pragma weak plat_arm_psci_override_pm_ops 18 #pragma weak plat_arm_program_trusted_mailbox 19 20 #if !ARM_RECOM_STATE_ID_ENC 21 /******************************************************************************* 22 * ARM standard platform handler called to check the validity of the power state 23 * parameter. 24 ******************************************************************************/ 25 int arm_validate_power_state(unsigned int power_state, 26 psci_power_state_t *req_state) 27 { 28 unsigned int pstate = psci_get_pstate_type(power_state); 29 unsigned int pwr_lvl = psci_get_pstate_pwrlvl(power_state); 30 unsigned int i; 31 32 assert(req_state != NULL); 33 34 if (pwr_lvl > PLAT_MAX_PWR_LVL) 35 return PSCI_E_INVALID_PARAMS; 36 37 /* Sanity check the requested state */ 38 if (pstate == PSTATE_TYPE_STANDBY) { 39 /* 40 * It's possible to enter standby only on power level 0 41 * Ignore any other power level. 42 */ 43 if (pwr_lvl != ARM_PWR_LVL0) 44 return PSCI_E_INVALID_PARAMS; 45 46 req_state->pwr_domain_state[ARM_PWR_LVL0] = 47 ARM_LOCAL_STATE_RET; 48 } else { 49 for (i = ARM_PWR_LVL0; i <= pwr_lvl; i++) 50 req_state->pwr_domain_state[i] = 51 ARM_LOCAL_STATE_OFF; 52 } 53 54 /* 55 * We expect the 'state id' to be zero. 56 */ 57 if (psci_get_pstate_id(power_state) != 0U) 58 return PSCI_E_INVALID_PARAMS; 59 60 return PSCI_E_SUCCESS; 61 } 62 63 #else 64 /******************************************************************************* 65 * ARM standard platform handler called to check the validity of the power 66 * state parameter. The power state parameter has to be a composite power 67 * state. 68 ******************************************************************************/ 69 int arm_validate_power_state(unsigned int power_state, 70 psci_power_state_t *req_state) 71 { 72 unsigned int state_id; 73 int i; 74 75 assert(req_state != NULL); 76 77 /* 78 * Currently we are using a linear search for finding the matching 79 * entry in the idle power state array. This can be made a binary 80 * search if the number of entries justify the additional complexity. 81 */ 82 for (i = 0; !!arm_pm_idle_states[i]; i++) { 83 if (power_state == arm_pm_idle_states[i]) 84 break; 85 } 86 87 /* Return error if entry not found in the idle state array */ 88 if (!arm_pm_idle_states[i]) 89 return PSCI_E_INVALID_PARAMS; 90 91 i = 0; 92 state_id = psci_get_pstate_id(power_state); 93 94 /* Parse the State ID and populate the state info parameter */ 95 while (state_id) { 96 req_state->pwr_domain_state[i++] = state_id & 97 ARM_LOCAL_PSTATE_MASK; 98 state_id >>= ARM_LOCAL_PSTATE_WIDTH; 99 } 100 101 return PSCI_E_SUCCESS; 102 } 103 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 104 105 /******************************************************************************* 106 * ARM standard platform handler called to check the validity of the non secure 107 * entrypoint. Returns 0 if the entrypoint is valid, or -1 otherwise. 108 ******************************************************************************/ 109 int arm_validate_ns_entrypoint(uintptr_t entrypoint) 110 { 111 /* 112 * Check if the non secure entrypoint lies within the non 113 * secure DRAM. 114 */ 115 if ((entrypoint >= ARM_NS_DRAM1_BASE) && (entrypoint < 116 (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) { 117 return 0; 118 } 119 #ifndef AARCH32 120 if ((entrypoint >= ARM_DRAM2_BASE) && (entrypoint < 121 (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) { 122 return 0; 123 } 124 #endif 125 126 return -1; 127 } 128 129 int arm_validate_psci_entrypoint(uintptr_t entrypoint) 130 { 131 return (arm_validate_ns_entrypoint(entrypoint) == 0) ? PSCI_E_SUCCESS : 132 PSCI_E_INVALID_ADDRESS; 133 } 134 135 /****************************************************************************** 136 * Default definition on ARM standard platforms to override the plat_psci_ops. 137 *****************************************************************************/ 138 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) 139 { 140 return ops; 141 } 142 143 /****************************************************************************** 144 * Helper function to save the platform state before a system suspend. Save the 145 * state of the system components which are not in the Always ON power domain. 146 *****************************************************************************/ 147 void arm_system_pwr_domain_save(void) 148 { 149 /* Assert system power domain is available on the platform */ 150 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); 151 152 plat_arm_gic_save(); 153 154 /* 155 * Unregister console now so that it is not registered for a second 156 * time during resume. 157 */ 158 arm_console_runtime_end(); 159 160 /* 161 * All the other peripheral which are configured by ARM TF are 162 * re-initialized on resume from system suspend. Hence we 163 * don't save their state here. 164 */ 165 } 166 167 /****************************************************************************** 168 * Helper function to resume the platform from system suspend. Reinitialize 169 * the system components which are not in the Always ON power domain. 170 * TODO: Unify the platform setup when waking up from cold boot and system 171 * resume in arm_bl31_platform_setup(). 172 *****************************************************************************/ 173 void arm_system_pwr_domain_resume(void) 174 { 175 /* Initialize the console */ 176 arm_console_runtime_init(); 177 178 /* Assert system power domain is available on the platform */ 179 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); 180 181 plat_arm_gic_resume(); 182 183 plat_arm_security_setup(); 184 arm_configure_sys_timer(); 185 } 186 187 /******************************************************************************* 188 * ARM platform function to program the mailbox for a cpu before it is released 189 * from reset. This function assumes that the Trusted mail box base is within 190 * the ARM_SHARED_RAM region 191 ******************************************************************************/ 192 void plat_arm_program_trusted_mailbox(uintptr_t address) 193 { 194 uintptr_t *mailbox = (void *) PLAT_ARM_TRUSTED_MAILBOX_BASE; 195 196 *mailbox = address; 197 198 /* 199 * Ensure that the PLAT_ARM_TRUSTED_MAILBOX_BASE is within 200 * ARM_SHARED_RAM region. 201 */ 202 assert((PLAT_ARM_TRUSTED_MAILBOX_BASE >= ARM_SHARED_RAM_BASE) && 203 ((PLAT_ARM_TRUSTED_MAILBOX_BASE + sizeof(*mailbox)) <= \ 204 (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE))); 205 } 206 207 /******************************************************************************* 208 * The ARM Standard platform definition of platform porting API 209 * `plat_setup_psci_ops`. 210 ******************************************************************************/ 211 int __init plat_setup_psci_ops(uintptr_t sec_entrypoint, 212 const plat_psci_ops_t **psci_ops) 213 { 214 *psci_ops = plat_arm_psci_override_pm_ops(&plat_arm_psci_pm_ops); 215 216 /* Setup mailbox with entry point. */ 217 plat_arm_program_trusted_mailbox(sec_entrypoint); 218 return 0; 219 } 220