1# 2# Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7ifeq (${ARCH}, aarch64) 8 # On ARM standard platorms, the TSP can execute from Trusted SRAM, Trusted 9 # DRAM (if available) or the TZC secured area of DRAM. 10 # TZC secured DRAM is the default. 11 12 ARM_TSP_RAM_LOCATION ?= dram 13 14 ifeq (${ARM_TSP_RAM_LOCATION}, tsram) 15 ARM_TSP_RAM_LOCATION_ID = ARM_TRUSTED_SRAM_ID 16 else ifeq (${ARM_TSP_RAM_LOCATION}, tdram) 17 ARM_TSP_RAM_LOCATION_ID = ARM_TRUSTED_DRAM_ID 18 else ifeq (${ARM_TSP_RAM_LOCATION}, dram) 19 ARM_TSP_RAM_LOCATION_ID = ARM_DRAM_ID 20 else 21 $(error "Unsupported ARM_TSP_RAM_LOCATION value") 22 endif 23 24 # Process flags 25 # Process ARM_BL31_IN_DRAM flag 26 ARM_BL31_IN_DRAM := 0 27 $(eval $(call assert_boolean,ARM_BL31_IN_DRAM)) 28 $(eval $(call add_define,ARM_BL31_IN_DRAM)) 29else 30 ARM_TSP_RAM_LOCATION_ID = ARM_TRUSTED_SRAM_ID 31endif 32 33$(eval $(call add_define,ARM_TSP_RAM_LOCATION_ID)) 34 35 36# For the original power-state parameter format, the State-ID can be encoded 37# according to the recommended encoding or zero. This flag determines which 38# State-ID encoding to be parsed. 39ARM_RECOM_STATE_ID_ENC := 0 40 41# If the PSCI_EXTENDED_STATE_ID is set, then ARM_RECOM_STATE_ID_ENC need to 42# be set. Else throw a build error. 43ifeq (${PSCI_EXTENDED_STATE_ID}, 1) 44 ifeq (${ARM_RECOM_STATE_ID_ENC}, 0) 45 $(error Build option ARM_RECOM_STATE_ID_ENC needs to be set if \ 46 PSCI_EXTENDED_STATE_ID is set for ARM platforms) 47 endif 48endif 49 50# Process ARM_RECOM_STATE_ID_ENC flag 51$(eval $(call assert_boolean,ARM_RECOM_STATE_ID_ENC)) 52$(eval $(call add_define,ARM_RECOM_STATE_ID_ENC)) 53 54# Process ARM_DISABLE_TRUSTED_WDOG flag 55# By default, Trusted Watchdog is always enabled unless SPIN_ON_BL1_EXIT is set 56ARM_DISABLE_TRUSTED_WDOG := 0 57ifeq (${SPIN_ON_BL1_EXIT}, 1) 58ARM_DISABLE_TRUSTED_WDOG := 1 59endif 60$(eval $(call assert_boolean,ARM_DISABLE_TRUSTED_WDOG)) 61$(eval $(call add_define,ARM_DISABLE_TRUSTED_WDOG)) 62 63# Process ARM_CONFIG_CNTACR 64ARM_CONFIG_CNTACR := 1 65$(eval $(call assert_boolean,ARM_CONFIG_CNTACR)) 66$(eval $(call add_define,ARM_CONFIG_CNTACR)) 67 68# Process ARM_BL31_IN_DRAM flag 69ARM_BL31_IN_DRAM := 0 70$(eval $(call assert_boolean,ARM_BL31_IN_DRAM)) 71$(eval $(call add_define,ARM_BL31_IN_DRAM)) 72 73# Process ARM_PLAT_MT flag 74ARM_PLAT_MT := 0 75$(eval $(call assert_boolean,ARM_PLAT_MT)) 76$(eval $(call add_define,ARM_PLAT_MT)) 77 78# Use translation tables library v2 by default 79ARM_XLAT_TABLES_LIB_V1 := 0 80$(eval $(call assert_boolean,ARM_XLAT_TABLES_LIB_V1)) 81$(eval $(call add_define,ARM_XLAT_TABLES_LIB_V1)) 82 83# Don't have the Linux kernel as a BL33 image by default 84ARM_LINUX_KERNEL_AS_BL33 := 0 85$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33)) 86$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33)) 87 88ifeq (${ARM_LINUX_KERNEL_AS_BL33},1) 89 ifeq (${ARCH},aarch64) 90 ifneq (${RESET_TO_BL31},1) 91 $(error "ARM_LINUX_KERNEL_AS_BL33 is only available if RESET_TO_BL31=1.") 92 endif 93 else 94 ifneq (${RESET_TO_SP_MIN},1) 95 $(error "ARM_LINUX_KERNEL_AS_BL33 is only available if RESET_TO_SP_MIN=1.") 96 endif 97 endif 98 ifndef PRELOADED_BL33_BASE 99 $(error "PRELOADED_BL33_BASE must be set if ARM_LINUX_KERNEL_AS_BL33 is used.") 100 endif 101 ifndef ARM_PRELOADED_DTB_BASE 102 $(error "ARM_PRELOADED_DTB_BASE must be set if ARM_LINUX_KERNEL_AS_BL33 is used.") 103 endif 104 $(eval $(call add_define,ARM_PRELOADED_DTB_BASE)) 105endif 106 107# Use an implementation of SHA-256 with a smaller memory footprint but reduced 108# speed. 109$(eval $(call add_define,MBEDTLS_SHA256_SMALLER)) 110 111# Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images 112# in the FIP if the platform requires. 113ifneq ($(BL32_EXTRA1),) 114$(eval $(call TOOL_ADD_IMG,bl32_extra1,--tos-fw-extra1)) 115endif 116ifneq ($(BL32_EXTRA2),) 117$(eval $(call TOOL_ADD_IMG,bl32_extra2,--tos-fw-extra2)) 118endif 119 120# Enable PSCI_STAT_COUNT/RESIDENCY APIs on ARM platforms 121ENABLE_PSCI_STAT := 1 122ENABLE_PMF := 1 123 124# On ARM platforms, separate the code and read-only data sections to allow 125# mapping the former as executable and the latter as execute-never. 126SEPARATE_CODE_AND_RODATA := 1 127 128# On ARM platforms, disable SEPARATE_NOBITS_REGION by default. Both PROGBITS 129# and NOBITS sections of BL31 image are adjacent to each other and loaded 130# into Trusted SRAM. 131SEPARATE_NOBITS_REGION := 0 132 133# In order to support SEPARATE_NOBITS_REGION for Arm platforms, we need to load 134# BL31 PROGBITS into secure DRAM space and BL31 NOBITS into SRAM. Hence mandate 135# the build to require that ARM_BL31_IN_DRAM is enabled as well. 136ifeq ($(SEPARATE_NOBITS_REGION),1) 137 ifneq ($(ARM_BL31_IN_DRAM),1) 138 $(error For SEPARATE_NOBITS_REGION, ARM_BL31_IN_DRAM must be enabled) 139 endif 140 ifneq ($(RECLAIM_INIT_CODE),0) 141 $(error For SEPARATE_NOBITS_REGION, RECLAIM_INIT_CODE cannot be supported) 142 endif 143endif 144 145# Disable ARM Cryptocell by default 146ARM_CRYPTOCELL_INTEG := 0 147$(eval $(call assert_boolean,ARM_CRYPTOCELL_INTEG)) 148$(eval $(call add_define,ARM_CRYPTOCELL_INTEG)) 149 150# Enable PIE support for RESET_TO_BL31 case 151ifeq (${RESET_TO_BL31},1) 152 ENABLE_PIE := 1 153endif 154 155# CryptoCell integration relies on coherent buffers for passing data from 156# the AP CPU to the CryptoCell 157ifeq (${ARM_CRYPTOCELL_INTEG},1) 158 ifeq (${USE_COHERENT_MEM},0) 159 $(error "ARM_CRYPTOCELL_INTEG needs USE_COHERENT_MEM to be set.") 160 endif 161endif 162 163ifeq (${ARCH}, aarch64) 164PLAT_INCLUDES += -Iinclude/plat/arm/common/aarch64 165endif 166 167PLAT_BL_COMMON_SOURCES += plat/arm/common/${ARCH}/arm_helpers.S \ 168 plat/arm/common/arm_common.c \ 169 plat/arm/common/arm_console.c 170 171ifeq (${ARM_XLAT_TABLES_LIB_V1}, 1) 172PLAT_BL_COMMON_SOURCES += lib/xlat_tables/xlat_tables_common.c \ 173 lib/xlat_tables/${ARCH}/xlat_tables.c 174else 175include lib/xlat_tables_v2/xlat_tables.mk 176 177PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} 178endif 179 180BL1_SOURCES += drivers/io/io_fip.c \ 181 drivers/io/io_memmap.c \ 182 drivers/io/io_storage.c \ 183 plat/arm/common/arm_bl1_setup.c \ 184 plat/arm/common/arm_err.c \ 185 plat/arm/common/arm_io_storage.c 186ifdef EL3_PAYLOAD_BASE 187# Need the plat_arm_program_trusted_mailbox() function to release secondary CPUs from 188# their holding pen 189BL1_SOURCES += plat/arm/common/arm_pm.c 190endif 191 192BL2_SOURCES += drivers/delay_timer/delay_timer.c \ 193 drivers/delay_timer/generic_delay_timer.c \ 194 drivers/io/io_fip.c \ 195 drivers/io/io_memmap.c \ 196 drivers/io/io_storage.c \ 197 plat/arm/common/arm_bl2_setup.c \ 198 plat/arm/common/arm_err.c \ 199 plat/arm/common/arm_io_storage.c 200 201# Add `libfdt` and Arm common helpers required for Dynamic Config 202include lib/libfdt/libfdt.mk 203 204DYN_CFG_SOURCES += plat/arm/common/arm_dyn_cfg.c \ 205 plat/arm/common/arm_dyn_cfg_helpers.c \ 206 common/fdt_wrappers.c 207 208BL1_SOURCES += ${DYN_CFG_SOURCES} 209BL2_SOURCES += ${DYN_CFG_SOURCES} 210 211ifeq (${BL2_AT_EL3},1) 212BL2_SOURCES += plat/arm/common/arm_bl2_el3_setup.c 213endif 214 215# Because BL1/BL2 execute in AArch64 mode but BL32 in AArch32 we need to use 216# the AArch32 descriptors. 217ifeq (${JUNO_AARCH32_EL3_RUNTIME},1) 218BL2_SOURCES += plat/arm/common/aarch32/arm_bl2_mem_params_desc.c 219else 220BL2_SOURCES += plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c 221endif 222BL2_SOURCES += plat/arm/common/arm_image_load.c \ 223 common/desc_image_load.c 224ifeq (${SPD},opteed) 225BL2_SOURCES += lib/optee/optee_utils.c 226endif 227 228BL2U_SOURCES += drivers/delay_timer/delay_timer.c \ 229 drivers/delay_timer/generic_delay_timer.c \ 230 plat/arm/common/arm_bl2u_setup.c 231 232BL31_SOURCES += plat/arm/common/arm_bl31_setup.c \ 233 plat/arm/common/arm_pm.c \ 234 plat/arm/common/arm_topology.c \ 235 plat/common/plat_psci_common.c 236 237ifeq (${ENABLE_PMF}, 1) 238ifeq (${ARCH}, aarch64) 239BL31_SOURCES += plat/arm/common/aarch64/execution_state_switch.c\ 240 plat/arm/common/arm_sip_svc.c \ 241 lib/pmf/pmf_smc.c 242else 243BL32_SOURCES += plat/arm/common/arm_sip_svc.c \ 244 lib/pmf/pmf_smc.c 245endif 246endif 247 248ifeq (${EL3_EXCEPTION_HANDLING},1) 249BL31_SOURCES += plat/arm/common/aarch64/arm_ehf.c 250endif 251 252ifeq (${SDEI_SUPPORT},1) 253BL31_SOURCES += plat/arm/common/aarch64/arm_sdei.c 254endif 255 256# RAS sources 257ifeq (${RAS_EXTENSION},1) 258BL31_SOURCES += lib/extensions/ras/std_err_record.c \ 259 lib/extensions/ras/ras_common.c 260endif 261 262# Pointer Authentication sources 263ifeq (${ENABLE_PAUTH}, 1) 264PLAT_BL_COMMON_SOURCES += plat/arm/common/aarch64/arm_pauth.c \ 265 lib/extensions/pauth/pauth_helpers.S 266endif 267 268ifneq (${TRUSTED_BOARD_BOOT},0) 269 270 # Include common TBB sources 271 AUTH_SOURCES := drivers/auth/auth_mod.c \ 272 drivers/auth/crypto_mod.c \ 273 drivers/auth/img_parser_mod.c \ 274 275 # Include the selected chain of trust sources. 276 ifeq (${COT},tbbr) 277 AUTH_SOURCES += drivers/auth/tbbr/tbbr_cot.c 278 else 279 $(error Unknown chain of trust ${COT}) 280 endif 281 282 BL1_SOURCES += ${AUTH_SOURCES} \ 283 bl1/tbbr/tbbr_img_desc.c \ 284 plat/arm/common/arm_bl1_fwu.c \ 285 plat/common/tbbr/plat_tbbr.c 286 287 BL2_SOURCES += ${AUTH_SOURCES} \ 288 plat/common/tbbr/plat_tbbr.c 289 290 $(eval $(call TOOL_ADD_IMG,ns_bl2u,--fwu,FWU_)) 291 292 # We expect to locate the *.mk files under the directories specified below 293ifeq (${ARM_CRYPTOCELL_INTEG},0) 294 CRYPTO_LIB_MK := drivers/auth/mbedtls/mbedtls_crypto.mk 295else 296 CRYPTO_LIB_MK := drivers/auth/cryptocell/cryptocell_crypto.mk 297endif 298 IMG_PARSER_LIB_MK := drivers/auth/mbedtls/mbedtls_x509.mk 299 300 $(info Including ${CRYPTO_LIB_MK}) 301 include ${CRYPTO_LIB_MK} 302 303 $(info Including ${IMG_PARSER_LIB_MK}) 304 include ${IMG_PARSER_LIB_MK} 305 306endif 307 308ifeq (${RECLAIM_INIT_CODE}, 1) 309 ifeq (${ARM_XLAT_TABLES_LIB_V1}, 1) 310 $(error "To reclaim init code xlat tables v2 must be used") 311 endif 312endif 313