1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <common/romlib.h> 15 #include <lib/mmio.h> 16 #include <lib/xlat_tables/xlat_tables_compat.h> 17 #include <plat/arm/common/plat_arm.h> 18 #include <plat/common/platform.h> 19 20 /* Weak definitions may be overridden in specific ARM standard platform */ 21 #pragma weak plat_get_ns_image_entrypoint 22 #pragma weak plat_arm_get_mmap 23 24 /* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid 25 * conflicts with the definition in plat/common. */ 26 #pragma weak plat_get_syscnt_freq2 27 28 29 void arm_setup_romlib(void) 30 { 31 #if USE_ROMLIB 32 if (!rom_lib_init(ROMLIB_VERSION)) 33 panic(); 34 #endif 35 } 36 37 uintptr_t plat_get_ns_image_entrypoint(void) 38 { 39 #ifdef PRELOADED_BL33_BASE 40 return PRELOADED_BL33_BASE; 41 #else 42 return PLAT_ARM_NS_IMAGE_BASE; 43 #endif 44 } 45 46 /******************************************************************************* 47 * Gets SPSR for BL32 entry 48 ******************************************************************************/ 49 uint32_t arm_get_spsr_for_bl32_entry(void) 50 { 51 /* 52 * The Secure Payload Dispatcher service is responsible for 53 * setting the SPSR prior to entry into the BL32 image. 54 */ 55 return 0; 56 } 57 58 /******************************************************************************* 59 * Gets SPSR for BL33 entry 60 ******************************************************************************/ 61 #ifdef __aarch64__ 62 uint32_t arm_get_spsr_for_bl33_entry(void) 63 { 64 unsigned int mode; 65 uint32_t spsr; 66 67 /* Figure out what mode we enter the non-secure world in */ 68 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1; 69 70 /* 71 * TODO: Consider the possibility of specifying the SPSR in 72 * the FIP ToC and allowing the platform to have a say as 73 * well. 74 */ 75 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 76 return spsr; 77 } 78 #else 79 /******************************************************************************* 80 * Gets SPSR for BL33 entry 81 ******************************************************************************/ 82 uint32_t arm_get_spsr_for_bl33_entry(void) 83 { 84 unsigned int hyp_status, mode, spsr; 85 86 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 87 88 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 89 90 /* 91 * TODO: Consider the possibility of specifying the SPSR in 92 * the FIP ToC and allowing the platform to have a say as 93 * well. 94 */ 95 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 96 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 97 return spsr; 98 } 99 #endif /* __aarch64__ */ 100 101 /******************************************************************************* 102 * Configures access to the system counter timer module. 103 ******************************************************************************/ 104 #ifdef ARM_SYS_TIMCTL_BASE 105 void arm_configure_sys_timer(void) 106 { 107 unsigned int reg_val; 108 109 /* Read the frequency of the system counter */ 110 unsigned int freq_val = plat_get_syscnt_freq2(); 111 112 #if ARM_CONFIG_CNTACR 113 reg_val = (1U << CNTACR_RPCT_SHIFT) | (1U << CNTACR_RVCT_SHIFT); 114 reg_val |= (1U << CNTACR_RFRQ_SHIFT) | (1U << CNTACR_RVOFF_SHIFT); 115 reg_val |= (1U << CNTACR_RWVT_SHIFT) | (1U << CNTACR_RWPT_SHIFT); 116 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val); 117 #endif /* ARM_CONFIG_CNTACR */ 118 119 reg_val = (1U << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); 120 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); 121 122 /* 123 * Initialize CNTFRQ register in CNTCTLBase frame. The CNTFRQ 124 * system register initialized during psci_arch_setup() is different 125 * from this and has to be updated independently. 126 */ 127 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val); 128 129 #if defined(PLAT_juno) || defined(PLAT_n1sdp) 130 /* 131 * Initialize CNTFRQ register in Non-secure CNTBase frame. 132 * This is only required for Juno and N1SDP, because they do not 133 * follow ARM ARM in that the value updated in CNTFRQ is not 134 * reflected in CNTBASEN_CNTFRQ. Hence update the value manually. 135 */ 136 mmio_write_32(ARM_SYS_CNT_BASE_NS + CNTBASEN_CNTFRQ, freq_val); 137 #endif 138 } 139 #endif /* ARM_SYS_TIMCTL_BASE */ 140 141 /******************************************************************************* 142 * Returns ARM platform specific memory map regions. 143 ******************************************************************************/ 144 const mmap_region_t *plat_arm_get_mmap(void) 145 { 146 return plat_arm_mmap; 147 } 148 149 #ifdef ARM_SYS_CNTCTL_BASE 150 151 unsigned int plat_get_syscnt_freq2(void) 152 { 153 unsigned int counter_base_frequency; 154 155 /* Read the frequency from Frequency modes table */ 156 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); 157 158 /* The first entry of the frequency modes table must not be 0 */ 159 if (counter_base_frequency == 0U) 160 panic(); 161 162 return counter_base_frequency; 163 } 164 165 #endif /* ARM_SYS_CNTCTL_BASE */ 166 167 #if SDEI_SUPPORT 168 /* 169 * Translate SDEI entry point to PA, and perform standard ARM entry point 170 * validation on it. 171 */ 172 int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode) 173 { 174 uint64_t par, pa; 175 u_register_t scr_el3; 176 177 /* Doing Non-secure address translation requires SCR_EL3.NS set */ 178 scr_el3 = read_scr_el3(); 179 write_scr_el3(scr_el3 | SCR_NS_BIT); 180 isb(); 181 182 assert((client_mode == MODE_EL2) || (client_mode == MODE_EL1)); 183 if (client_mode == MODE_EL2) { 184 /* 185 * Translate entry point to Physical Address using the EL2 186 * translation regime. 187 */ 188 ats1e2r(ep); 189 } else { 190 /* 191 * Translate entry point to Physical Address using the EL1&0 192 * translation regime, including stage 2. 193 */ 194 ats12e1r(ep); 195 } 196 isb(); 197 par = read_par_el1(); 198 199 /* Restore original SCRL_EL3 */ 200 write_scr_el3(scr_el3); 201 isb(); 202 203 /* If the translation resulted in fault, return failure */ 204 if ((par & PAR_F_MASK) != 0) 205 return -1; 206 207 /* Extract Physical Address from PAR */ 208 pa = (par & (PAR_ADDR_MASK << PAR_ADDR_SHIFT)); 209 210 /* Perform NS entry point validation on the physical address */ 211 return arm_validate_ns_entrypoint(pa); 212 } 213 #endif 214