1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <common/romlib.h> 15 #include <lib/mmio.h> 16 #include <lib/xlat_tables/xlat_tables_compat.h> 17 #include <plat/common/platform.h> 18 #include <services/secure_partition.h> 19 20 #include <plat_arm.h> 21 22 /* Weak definitions may be overridden in specific ARM standard platform */ 23 #pragma weak plat_get_ns_image_entrypoint 24 #pragma weak plat_arm_get_mmap 25 26 /* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid 27 * conflicts with the definition in plat/common. */ 28 #pragma weak plat_get_syscnt_freq2 29 30 31 void arm_setup_romlib(void) 32 { 33 #if USE_ROMLIB 34 if (!rom_lib_init(ROMLIB_VERSION)) 35 panic(); 36 #endif 37 } 38 39 uintptr_t plat_get_ns_image_entrypoint(void) 40 { 41 #ifdef PRELOADED_BL33_BASE 42 return PRELOADED_BL33_BASE; 43 #else 44 return PLAT_ARM_NS_IMAGE_OFFSET; 45 #endif 46 } 47 48 /******************************************************************************* 49 * Gets SPSR for BL32 entry 50 ******************************************************************************/ 51 uint32_t arm_get_spsr_for_bl32_entry(void) 52 { 53 /* 54 * The Secure Payload Dispatcher service is responsible for 55 * setting the SPSR prior to entry into the BL32 image. 56 */ 57 return 0; 58 } 59 60 /******************************************************************************* 61 * Gets SPSR for BL33 entry 62 ******************************************************************************/ 63 #ifndef AARCH32 64 uint32_t arm_get_spsr_for_bl33_entry(void) 65 { 66 unsigned int mode; 67 uint32_t spsr; 68 69 /* Figure out what mode we enter the non-secure world in */ 70 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1; 71 72 /* 73 * TODO: Consider the possibility of specifying the SPSR in 74 * the FIP ToC and allowing the platform to have a say as 75 * well. 76 */ 77 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 78 return spsr; 79 } 80 #else 81 /******************************************************************************* 82 * Gets SPSR for BL33 entry 83 ******************************************************************************/ 84 uint32_t arm_get_spsr_for_bl33_entry(void) 85 { 86 unsigned int hyp_status, mode, spsr; 87 88 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 89 90 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 91 92 /* 93 * TODO: Consider the possibility of specifying the SPSR in 94 * the FIP ToC and allowing the platform to have a say as 95 * well. 96 */ 97 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 98 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 99 return spsr; 100 } 101 #endif /* AARCH32 */ 102 103 /******************************************************************************* 104 * Configures access to the system counter timer module. 105 ******************************************************************************/ 106 #ifdef ARM_SYS_TIMCTL_BASE 107 void arm_configure_sys_timer(void) 108 { 109 unsigned int reg_val; 110 111 /* Read the frequency of the system counter */ 112 unsigned int freq_val = plat_get_syscnt_freq2(); 113 114 #if ARM_CONFIG_CNTACR 115 reg_val = (1U << CNTACR_RPCT_SHIFT) | (1U << CNTACR_RVCT_SHIFT); 116 reg_val |= (1U << CNTACR_RFRQ_SHIFT) | (1U << CNTACR_RVOFF_SHIFT); 117 reg_val |= (1U << CNTACR_RWVT_SHIFT) | (1U << CNTACR_RWPT_SHIFT); 118 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val); 119 #endif /* ARM_CONFIG_CNTACR */ 120 121 reg_val = (1U << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); 122 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); 123 124 /* 125 * Initialize CNTFRQ register in CNTCTLBase frame. The CNTFRQ 126 * system register initialized during psci_arch_setup() is different 127 * from this and has to be updated independently. 128 */ 129 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val); 130 131 #ifdef PLAT_juno 132 /* 133 * Initialize CNTFRQ register in Non-secure CNTBase frame. 134 * This is only required for Juno, because it doesn't follow ARM ARM 135 * in that the value updated in CNTFRQ is not reflected in 136 * CNTBASEN_CNTFRQ. Hence update the value manually. 137 */ 138 mmio_write_32(ARM_SYS_CNT_BASE_NS + CNTBASEN_CNTFRQ, freq_val); 139 #endif 140 } 141 #endif /* ARM_SYS_TIMCTL_BASE */ 142 143 /******************************************************************************* 144 * Returns ARM platform specific memory map regions. 145 ******************************************************************************/ 146 const mmap_region_t *plat_arm_get_mmap(void) 147 { 148 return plat_arm_mmap; 149 } 150 151 #ifdef ARM_SYS_CNTCTL_BASE 152 153 unsigned int plat_get_syscnt_freq2(void) 154 { 155 unsigned int counter_base_frequency; 156 157 /* Read the frequency from Frequency modes table */ 158 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); 159 160 /* The first entry of the frequency modes table must not be 0 */ 161 if (counter_base_frequency == 0U) 162 panic(); 163 164 return counter_base_frequency; 165 } 166 167 #endif /* ARM_SYS_CNTCTL_BASE */ 168 169 #if SDEI_SUPPORT 170 /* 171 * Translate SDEI entry point to PA, and perform standard ARM entry point 172 * validation on it. 173 */ 174 int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode) 175 { 176 uint64_t par, pa; 177 uint32_t scr_el3; 178 179 /* Doing Non-secure address translation requires SCR_EL3.NS set */ 180 scr_el3 = read_scr_el3(); 181 write_scr_el3(scr_el3 | SCR_NS_BIT); 182 isb(); 183 184 assert((client_mode == MODE_EL2) || (client_mode == MODE_EL1)); 185 if (client_mode == MODE_EL2) { 186 /* 187 * Translate entry point to Physical Address using the EL2 188 * translation regime. 189 */ 190 ats1e2r(ep); 191 } else { 192 /* 193 * Translate entry point to Physical Address using the EL1&0 194 * translation regime, including stage 2. 195 */ 196 ats12e1r(ep); 197 } 198 isb(); 199 par = read_par_el1(); 200 201 /* Restore original SCRL_EL3 */ 202 write_scr_el3(scr_el3); 203 isb(); 204 205 /* If the translation resulted in fault, return failure */ 206 if ((par & PAR_F_MASK) != 0) 207 return -1; 208 209 /* Extract Physical Address from PAR */ 210 pa = (par & (PAR_ADDR_MASK << PAR_ADDR_SHIFT)); 211 212 /* Perform NS entry point validation on the physical address */ 213 return arm_validate_ns_entrypoint(pa); 214 } 215 #endif 216