1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <common/romlib.h> 15 #include <lib/mmio.h> 16 #include <lib/smccc.h> 17 #include <lib/xlat_tables/xlat_tables_compat.h> 18 #include <services/arm_arch_svc.h> 19 #include <plat/arm/common/plat_arm.h> 20 #include <plat/common/platform.h> 21 22 /* Weak definitions may be overridden in specific ARM standard platform */ 23 #pragma weak plat_get_ns_image_entrypoint 24 #pragma weak plat_arm_get_mmap 25 26 /* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid 27 * conflicts with the definition in plat/common. */ 28 #pragma weak plat_get_syscnt_freq2 29 30 /* Get ARM SOC-ID */ 31 #pragma weak plat_arm_get_soc_id 32 33 /******************************************************************************* 34 * Changes the memory attributes for the region of mapped memory where the BL 35 * image's translation tables are located such that the tables will have 36 * read-only permissions. 37 ******************************************************************************/ 38 #if PLAT_RO_XLAT_TABLES 39 void arm_xlat_make_tables_readonly(void) 40 { 41 int rc = xlat_make_tables_readonly(); 42 43 if (rc != 0) { 44 ERROR("Failed to make translation tables read-only at EL%u.\n", 45 get_current_el()); 46 panic(); 47 } 48 49 INFO("Translation tables are now read-only at EL%u.\n", 50 get_current_el()); 51 } 52 #endif 53 54 void arm_setup_romlib(void) 55 { 56 #if USE_ROMLIB 57 if (!rom_lib_init(ROMLIB_VERSION)) 58 panic(); 59 #endif 60 } 61 62 uintptr_t plat_get_ns_image_entrypoint(void) 63 { 64 #ifdef PRELOADED_BL33_BASE 65 return PRELOADED_BL33_BASE; 66 #else 67 return PLAT_ARM_NS_IMAGE_BASE; 68 #endif 69 } 70 71 /******************************************************************************* 72 * Gets SPSR for BL32 entry 73 ******************************************************************************/ 74 uint32_t arm_get_spsr_for_bl32_entry(void) 75 { 76 /* 77 * The Secure Payload Dispatcher service is responsible for 78 * setting the SPSR prior to entry into the BL32 image. 79 */ 80 return 0; 81 } 82 83 /******************************************************************************* 84 * Gets SPSR for BL33 entry 85 ******************************************************************************/ 86 #ifdef __aarch64__ 87 uint32_t arm_get_spsr_for_bl33_entry(void) 88 { 89 unsigned int mode; 90 uint32_t spsr; 91 92 /* Figure out what mode we enter the non-secure world in */ 93 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1; 94 95 /* 96 * TODO: Consider the possibility of specifying the SPSR in 97 * the FIP ToC and allowing the platform to have a say as 98 * well. 99 */ 100 spsr = SPSR_64((uint64_t)mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 101 return spsr; 102 } 103 #else 104 /******************************************************************************* 105 * Gets SPSR for BL33 entry 106 ******************************************************************************/ 107 uint32_t arm_get_spsr_for_bl33_entry(void) 108 { 109 unsigned int hyp_status, mode, spsr; 110 111 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 112 113 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 114 115 /* 116 * TODO: Consider the possibility of specifying the SPSR in 117 * the FIP ToC and allowing the platform to have a say as 118 * well. 119 */ 120 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 121 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 122 return spsr; 123 } 124 #endif /* __aarch64__ */ 125 126 /******************************************************************************* 127 * Configures access to the system counter timer module. 128 ******************************************************************************/ 129 #ifdef ARM_SYS_TIMCTL_BASE 130 void arm_configure_sys_timer(void) 131 { 132 unsigned int reg_val; 133 134 /* Read the frequency of the system counter */ 135 unsigned int freq_val = plat_get_syscnt_freq2(); 136 137 #if ARM_CONFIG_CNTACR 138 reg_val = (1U << CNTACR_RPCT_SHIFT) | (1U << CNTACR_RVCT_SHIFT); 139 reg_val |= (1U << CNTACR_RFRQ_SHIFT) | (1U << CNTACR_RVOFF_SHIFT); 140 reg_val |= (1U << CNTACR_RWVT_SHIFT) | (1U << CNTACR_RWPT_SHIFT); 141 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val); 142 #endif /* ARM_CONFIG_CNTACR */ 143 144 reg_val = (1U << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); 145 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); 146 147 /* 148 * Initialize CNTFRQ register in CNTCTLBase frame. The CNTFRQ 149 * system register initialized during psci_arch_setup() is different 150 * from this and has to be updated independently. 151 */ 152 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val); 153 154 #if defined(PLAT_juno) || defined(PLAT_n1sdp) 155 /* 156 * Initialize CNTFRQ register in Non-secure CNTBase frame. 157 * This is only required for Juno and N1SDP, because they do not 158 * follow ARM ARM in that the value updated in CNTFRQ is not 159 * reflected in CNTBASEN_CNTFRQ. Hence update the value manually. 160 */ 161 mmio_write_32(ARM_SYS_CNT_BASE_NS + CNTBASEN_CNTFRQ, freq_val); 162 #endif 163 } 164 #endif /* ARM_SYS_TIMCTL_BASE */ 165 166 /******************************************************************************* 167 * Returns ARM platform specific memory map regions. 168 ******************************************************************************/ 169 const mmap_region_t *plat_arm_get_mmap(void) 170 { 171 return plat_arm_mmap; 172 } 173 174 #ifdef ARM_SYS_CNTCTL_BASE 175 176 unsigned int plat_get_syscnt_freq2(void) 177 { 178 unsigned int counter_base_frequency; 179 180 /* Read the frequency from Frequency modes table */ 181 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); 182 183 /* The first entry of the frequency modes table must not be 0 */ 184 if (counter_base_frequency == 0U) 185 panic(); 186 187 return counter_base_frequency; 188 } 189 190 #endif /* ARM_SYS_CNTCTL_BASE */ 191 192 #if SDEI_SUPPORT 193 /* 194 * Translate SDEI entry point to PA, and perform standard ARM entry point 195 * validation on it. 196 */ 197 int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode) 198 { 199 uint64_t par, pa; 200 u_register_t scr_el3; 201 202 /* Doing Non-secure address translation requires SCR_EL3.NS set */ 203 scr_el3 = read_scr_el3(); 204 write_scr_el3(scr_el3 | SCR_NS_BIT); 205 isb(); 206 207 assert((client_mode == MODE_EL2) || (client_mode == MODE_EL1)); 208 if (client_mode == MODE_EL2) { 209 /* 210 * Translate entry point to Physical Address using the EL2 211 * translation regime. 212 */ 213 ats1e2r(ep); 214 } else { 215 /* 216 * Translate entry point to Physical Address using the EL1&0 217 * translation regime, including stage 2. 218 */ 219 AT(ats12e1r, ep); 220 } 221 isb(); 222 par = read_par_el1(); 223 224 /* Restore original SCRL_EL3 */ 225 write_scr_el3(scr_el3); 226 isb(); 227 228 /* If the translation resulted in fault, return failure */ 229 if ((par & PAR_F_MASK) != 0) 230 return -1; 231 232 /* Extract Physical Address from PAR */ 233 pa = (par & (PAR_ADDR_MASK << PAR_ADDR_SHIFT)); 234 235 /* Perform NS entry point validation on the physical address */ 236 return arm_validate_ns_entrypoint(pa); 237 } 238 #endif 239 240