1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <arch.h> 7 #include <arch_helpers.h> 8 #include <arm_xlat_tables.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <mmio.h> 12 #include <plat_arm.h> 13 #include <platform_def.h> 14 #include <secure_partition.h> 15 16 extern const mmap_region_t plat_arm_mmap[]; 17 18 /* Weak definitions may be overridden in specific ARM standard platform */ 19 #pragma weak plat_get_ns_image_entrypoint 20 #pragma weak plat_arm_get_mmap 21 22 /* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid 23 * conflicts with the definition in plat/common. */ 24 #if ERROR_DEPRECATED 25 #pragma weak plat_get_syscnt_freq2 26 #endif 27 28 /* 29 * Set up the page tables for the generic and platform-specific memory regions. 30 * The extents of the generic memory regions are specified by the function 31 * arguments and consist of: 32 * - Trusted SRAM seen by the BL image; 33 * - Code section; 34 * - Read-only data section; 35 * - Coherent memory region, if applicable. 36 */ 37 void arm_setup_page_tables(uintptr_t total_base, 38 size_t total_size, 39 uintptr_t code_start, 40 uintptr_t code_limit, 41 uintptr_t rodata_start, 42 uintptr_t rodata_limit 43 #if USE_COHERENT_MEM 44 , 45 uintptr_t coh_start, 46 uintptr_t coh_limit 47 #endif 48 ) 49 { 50 /* 51 * Map the Trusted SRAM with appropriate memory attributes. 52 * Subsequent mappings will adjust the attributes for specific regions. 53 */ 54 VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n", 55 (void *) total_base, (void *) (total_base + total_size)); 56 mmap_add_region(total_base, total_base, 57 total_size, 58 MT_MEMORY | MT_RW | MT_SECURE); 59 60 /* Re-map the code section */ 61 VERBOSE("Code region: %p - %p\n", 62 (void *) code_start, (void *) code_limit); 63 mmap_add_region(code_start, code_start, 64 code_limit - code_start, 65 MT_CODE | MT_SECURE); 66 67 /* Re-map the read-only data section */ 68 VERBOSE("Read-only data region: %p - %p\n", 69 (void *) rodata_start, (void *) rodata_limit); 70 mmap_add_region(rodata_start, rodata_start, 71 rodata_limit - rodata_start, 72 MT_RO_DATA | MT_SECURE); 73 74 #if USE_COHERENT_MEM 75 /* Re-map the coherent memory region */ 76 VERBOSE("Coherent region: %p - %p\n", 77 (void *) coh_start, (void *) coh_limit); 78 mmap_add_region(coh_start, coh_start, 79 coh_limit - coh_start, 80 MT_DEVICE | MT_RW | MT_SECURE); 81 #endif 82 83 #if ENABLE_SPM && defined(IMAGE_BL31) 84 /* The address of the following region is calculated by the linker. */ 85 mmap_add_region(SP_IMAGE_XLAT_TABLES_START, 86 SP_IMAGE_XLAT_TABLES_START, 87 SP_IMAGE_XLAT_TABLES_SIZE, 88 MT_MEMORY | MT_RW | MT_SECURE); 89 #endif 90 91 /* Now (re-)map the platform-specific memory regions */ 92 mmap_add(plat_arm_get_mmap()); 93 94 /* Create the page tables to reflect the above mappings */ 95 init_xlat_tables(); 96 } 97 98 uintptr_t plat_get_ns_image_entrypoint(void) 99 { 100 #ifdef PRELOADED_BL33_BASE 101 return PRELOADED_BL33_BASE; 102 #else 103 return PLAT_ARM_NS_IMAGE_OFFSET; 104 #endif 105 } 106 107 /******************************************************************************* 108 * Gets SPSR for BL32 entry 109 ******************************************************************************/ 110 uint32_t arm_get_spsr_for_bl32_entry(void) 111 { 112 /* 113 * The Secure Payload Dispatcher service is responsible for 114 * setting the SPSR prior to entry into the BL32 image. 115 */ 116 return 0; 117 } 118 119 /******************************************************************************* 120 * Gets SPSR for BL33 entry 121 ******************************************************************************/ 122 #ifndef AARCH32 123 uint32_t arm_get_spsr_for_bl33_entry(void) 124 { 125 unsigned int mode; 126 uint32_t spsr; 127 128 /* Figure out what mode we enter the non-secure world in */ 129 mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1; 130 131 /* 132 * TODO: Consider the possibility of specifying the SPSR in 133 * the FIP ToC and allowing the platform to have a say as 134 * well. 135 */ 136 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 137 return spsr; 138 } 139 #else 140 /******************************************************************************* 141 * Gets SPSR for BL33 entry 142 ******************************************************************************/ 143 uint32_t arm_get_spsr_for_bl33_entry(void) 144 { 145 unsigned int hyp_status, mode, spsr; 146 147 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 148 149 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 150 151 /* 152 * TODO: Consider the possibility of specifying the SPSR in 153 * the FIP ToC and allowing the platform to have a say as 154 * well. 155 */ 156 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 157 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 158 return spsr; 159 } 160 #endif /* AARCH32 */ 161 162 /******************************************************************************* 163 * Configures access to the system counter timer module. 164 ******************************************************************************/ 165 #ifdef ARM_SYS_TIMCTL_BASE 166 void arm_configure_sys_timer(void) 167 { 168 unsigned int reg_val; 169 170 #if ARM_CONFIG_CNTACR 171 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); 172 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); 173 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); 174 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val); 175 #endif /* ARM_CONFIG_CNTACR */ 176 177 reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); 178 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); 179 } 180 #endif /* ARM_SYS_TIMCTL_BASE */ 181 182 /******************************************************************************* 183 * Returns ARM platform specific memory map regions. 184 ******************************************************************************/ 185 const mmap_region_t *plat_arm_get_mmap(void) 186 { 187 return plat_arm_mmap; 188 } 189 190 #ifdef ARM_SYS_CNTCTL_BASE 191 192 unsigned int plat_get_syscnt_freq2(void) 193 { 194 unsigned int counter_base_frequency; 195 196 /* Read the frequency from Frequency modes table */ 197 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); 198 199 /* The first entry of the frequency modes table must not be 0 */ 200 if (counter_base_frequency == 0) 201 panic(); 202 203 return counter_base_frequency; 204 } 205 206 #endif /* ARM_SYS_CNTCTL_BASE */ 207 208 #if SDEI_SUPPORT 209 /* 210 * Translate SDEI entry point to PA, and perform standard ARM entry point 211 * validation on it. 212 */ 213 int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode) 214 { 215 uint64_t par, pa; 216 uint32_t scr_el3; 217 218 /* Doing Non-secure address translation requires SCR_EL3.NS set */ 219 scr_el3 = read_scr_el3(); 220 write_scr_el3(scr_el3 | SCR_NS_BIT); 221 isb(); 222 223 assert((client_mode == MODE_EL2) || (client_mode == MODE_EL1)); 224 if (client_mode == MODE_EL2) { 225 /* 226 * Translate entry point to Physical Address using the EL2 227 * translation regime. 228 */ 229 ats1e2r(ep); 230 } else { 231 /* 232 * Translate entry point to Physical Address using the EL1&0 233 * translation regime, including stage 2. 234 */ 235 ats12e1r(ep); 236 } 237 isb(); 238 par = read_par_el1(); 239 240 /* Restore original SCRL_EL3 */ 241 write_scr_el3(scr_el3); 242 isb(); 243 244 /* If the translation resulted in fault, return failure */ 245 if ((par & PAR_F_MASK) != 0) 246 return -1; 247 248 /* Extract Physical Address from PAR */ 249 pa = (par & (PAR_ADDR_MASK << PAR_ADDR_SHIFT)); 250 251 /* Perform NS entry point validation on the physical address */ 252 return arm_validate_ns_entrypoint(pa); 253 } 254 #endif 255