1 /* 2 * Copyright (c) 2015-2026, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <common/romlib.h> 15 #include <common/par.h> 16 #include <lib/extensions/sysreg128.h> 17 #include <lib/mmio.h> 18 #include <lib/smccc.h> 19 #include <lib/xlat_tables/xlat_tables_compat.h> 20 #include <services/arm_arch_svc.h> 21 #include <plat/arm/common/plat_arm.h> 22 #include <plat/common/platform.h> 23 24 /* Weak definitions may be overridden in specific ARM standard platform */ 25 #pragma weak plat_get_ns_image_entrypoint 26 #pragma weak plat_arm_get_mmap 27 28 /* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid 29 * conflicts with the definition in plat/common. */ 30 #pragma weak plat_get_syscnt_freq2 31 32 /* Get ARM SOC-ID */ 33 #pragma weak plat_arm_get_soc_id 34 35 #if USE_GIC_DRIVER == 3 36 uintptr_t arm_gicr_base_addrs[2] = { 37 PLAT_ARM_GICR_BASE, /* GICR Base address of the primary CPU */ 38 0U /* Zero Termination */ 39 }; 40 #endif 41 42 /******************************************************************************* 43 * Changes the memory attributes for the region of mapped memory where the BL 44 * image's translation tables are located such that the tables will have 45 * read-only permissions. 46 ******************************************************************************/ 47 #if PLAT_RO_XLAT_TABLES 48 void arm_xlat_make_tables_readonly(void) 49 { 50 int rc = xlat_make_tables_readonly(); 51 52 if (rc != 0) { 53 ERROR("Failed to make translation tables read-only at EL%u.\n", 54 get_current_el()); 55 panic(); 56 } 57 58 INFO("Translation tables are now read-only at EL%u.\n", 59 get_current_el()); 60 } 61 #endif 62 63 void arm_setup_romlib(void) 64 { 65 #if USE_ROMLIB 66 if (!rom_lib_init(ROMLIB_VERSION)) 67 panic(); 68 #endif 69 } 70 71 uintptr_t plat_get_ns_image_entrypoint(void) 72 { 73 #ifdef PRELOADED_BL33_BASE 74 return PRELOADED_BL33_BASE; 75 #else 76 return PLAT_ARM_NS_IMAGE_BASE; 77 #endif 78 } 79 80 /******************************************************************************* 81 * Gets SPSR for next stage images. 82 ******************************************************************************/ 83 uint32_t arm_get_spsr(unsigned int image_id) 84 { 85 unsigned int __unused hyp_status, mode, spsr; 86 87 if (image_id == BL32_IMAGE_ID) { 88 /* The Secure Payload Dispatcher service is responsible for 89 * setting the SPSR prior to entry into the BL32 image. 90 */ 91 return 0; 92 } 93 94 #ifdef __aarch64__ 95 /* Figure out what mode we enter the non-secure world in */ 96 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1; 97 98 /* 99 * TODO: Consider the possibility of specifying the SPSR in 100 * the FIP ToC and allowing the platform to have a say as 101 * well. 102 */ 103 spsr = SPSR_64((uint64_t)mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 104 #else 105 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 106 107 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 108 109 /* 110 * TODO: Consider the possibility of specifying the SPSR in 111 * the FIP ToC and allowing the platform to have a say as 112 * well. 113 */ 114 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 115 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 116 #endif /* __aarch64__ */ 117 118 return spsr; 119 } 120 121 /******************************************************************************* 122 * Configures access to the system counter timer module. 123 ******************************************************************************/ 124 #ifdef ARM_SYS_TIMCTL_BASE 125 void arm_configure_sys_timer(void) 126 { 127 unsigned int reg_val; 128 129 /* Read the frequency of the system counter */ 130 unsigned int freq_val = plat_get_syscnt_freq2(); 131 132 #if ARM_CONFIG_CNTACR 133 reg_val = (1U << CNTACR_RPCT_SHIFT) | (1U << CNTACR_RVCT_SHIFT); 134 reg_val |= (1U << CNTACR_RFRQ_SHIFT) | (1U << CNTACR_RVOFF_SHIFT); 135 reg_val |= (1U << CNTACR_RWVT_SHIFT) | (1U << CNTACR_RWPT_SHIFT); 136 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val); 137 #endif /* ARM_CONFIG_CNTACR */ 138 139 reg_val = (1U << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); 140 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); 141 142 /* 143 * Initialize CNTFRQ register in CNTCTLBase frame. The CNTFRQ 144 * system register initialized during psci_arch_setup() is different 145 * from this and has to be updated independently. 146 */ 147 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val); 148 149 #if defined(PLAT_juno) || defined(PLAT_n1sdp) || defined(PLAT_morello) 150 /* 151 * Initialize CNTFRQ register in Non-secure CNTBase frame. 152 * This is required for Juno, N1SDP and Morello because they do not 153 * follow ARM ARM in that the value updated in CNTFRQ is not 154 * reflected in CNTBASEN_CNTFRQ. Hence update the value manually. 155 */ 156 mmio_write_32(ARM_SYS_CNT_BASE_NS + CNTBASEN_CNTFRQ, freq_val); 157 #endif 158 } 159 #endif /* ARM_SYS_TIMCTL_BASE */ 160 161 /******************************************************************************* 162 * Returns ARM platform specific memory map regions. 163 ******************************************************************************/ 164 const mmap_region_t *plat_arm_get_mmap(void) 165 { 166 return plat_arm_mmap; 167 } 168 169 #ifdef ARM_SYS_CNTCTL_BASE 170 171 unsigned int plat_get_syscnt_freq2(void) 172 { 173 unsigned int counter_base_frequency; 174 175 /* Read the frequency from Frequency modes table */ 176 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); 177 178 /* The first entry of the frequency modes table must not be 0 */ 179 if (counter_base_frequency == 0U) 180 panic(); 181 182 return counter_base_frequency; 183 } 184 185 #endif /* ARM_SYS_CNTCTL_BASE */ 186 187 #if SDEI_SUPPORT 188 /* 189 * Translate SDEI entry point to PA, and perform standard ARM entry point 190 * validation on it. 191 */ 192 int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode) 193 { 194 uint64_t pa; 195 sysreg_t par; 196 u_register_t scr_el3; 197 198 /* Doing Non-secure address translation requires SCR_EL3.NS set */ 199 scr_el3 = read_scr_el3(); 200 write_scr_el3(scr_el3 | SCR_NS_BIT); 201 isb(); 202 203 assert((client_mode == MODE_EL2) || (client_mode == MODE_EL1)); 204 if (client_mode == MODE_EL2) { 205 /* 206 * Translate entry point to Physical Address using the EL2 207 * translation regime. 208 */ 209 ats1e2r(ep); 210 } else { 211 /* 212 * Translate entry point to Physical Address using the EL1&0 213 * translation regime, including stage 2. 214 */ 215 AT(ats12e1r, ep); 216 } 217 isb(); 218 par = read_par_el1(); 219 220 /* Restore original SCRL_EL3 */ 221 write_scr_el3(scr_el3); 222 isb(); 223 224 /* If the translation resulted in fault, return failure */ 225 if ((par & PAR_F_MASK) != 0) 226 return -1; 227 228 /* Extract Physical Address from PAR */ 229 pa = get_par_el1_pa(par); 230 231 /* Perform NS entry point validation on the physical address */ 232 return arm_validate_ns_entrypoint(pa); 233 } 234 #endif 235 236 const mmap_region_t *plat_get_addr_mmap(void) 237 { 238 return plat_arm_mmap; 239 } 240 241 #if ENABLE_RME 242 void arm_gpt_setup(void) 243 { 244 /* 245 * It is to be noted that any Arm platform that reuses arm_gpt_setup 246 * must implement plat_arm_get_gpt_info within its platform code 247 */ 248 const arm_gpt_info_t *arm_gpt_info = 249 plat_arm_get_gpt_info(); 250 251 if (arm_gpt_info == NULL) { 252 ERROR("arm_gpt_info not initialized!!\n"); 253 panic(); 254 } 255 256 /* Initialize entire protected space to GPT_GPI_ANY. */ 257 if (gpt_init_l0_tables(arm_gpt_info->pps, arm_gpt_info->l0_base, 258 arm_gpt_info->l0_size) < 0) { 259 ERROR("gpt_init_l0_tables() failed!\n"); 260 panic(); 261 } 262 263 /* Carve out defined PAS ranges. */ 264 if (gpt_init_pas_l1_tables(arm_gpt_info->pgs, 265 arm_gpt_info->l1_base, 266 arm_gpt_info->l1_size, 267 arm_gpt_info->pas_region_base, 268 arm_gpt_info->pas_region_count) < 0) { 269 ERROR("gpt_init_pas_l1_tables() failed!\n"); 270 panic(); 271 } 272 273 INFO("Enabling Granule Protection Checks\n"); 274 if (gpt_enable() < 0) { 275 ERROR("gpt_enable() failed!\n"); 276 panic(); 277 } 278 } 279 #endif /* ENABLE_RME */ 280