1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <common/romlib.h> 15 #include <lib/mmio.h> 16 #include <lib/xlat_tables/xlat_tables_compat.h> 17 #include <plat/arm/common/plat_arm.h> 18 #include <plat/common/platform.h> 19 20 /* Weak definitions may be overridden in specific ARM standard platform */ 21 #pragma weak plat_get_ns_image_entrypoint 22 #pragma weak plat_arm_get_mmap 23 24 /* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid 25 * conflicts with the definition in plat/common. */ 26 #pragma weak plat_get_syscnt_freq2 27 28 /******************************************************************************* 29 * Changes the memory attributes for the region of mapped memory where the BL 30 * image's translation tables are located such that the tables will have 31 * read-only permissions. 32 ******************************************************************************/ 33 #if PLAT_RO_XLAT_TABLES 34 void arm_xlat_make_tables_readonly(void) 35 { 36 int rc = xlat_make_tables_readonly(); 37 38 if (rc != 0) { 39 ERROR("Failed to make translation tables read-only at EL%u.\n", 40 get_current_el()); 41 panic(); 42 } 43 44 INFO("Translation tables are now read-only at EL%u.\n", 45 get_current_el()); 46 } 47 #endif 48 49 void arm_setup_romlib(void) 50 { 51 #if USE_ROMLIB 52 if (!rom_lib_init(ROMLIB_VERSION)) 53 panic(); 54 #endif 55 } 56 57 uintptr_t plat_get_ns_image_entrypoint(void) 58 { 59 #ifdef PRELOADED_BL33_BASE 60 return PRELOADED_BL33_BASE; 61 #else 62 return PLAT_ARM_NS_IMAGE_BASE; 63 #endif 64 } 65 66 /******************************************************************************* 67 * Gets SPSR for BL32 entry 68 ******************************************************************************/ 69 uint32_t arm_get_spsr_for_bl32_entry(void) 70 { 71 /* 72 * The Secure Payload Dispatcher service is responsible for 73 * setting the SPSR prior to entry into the BL32 image. 74 */ 75 return 0; 76 } 77 78 /******************************************************************************* 79 * Gets SPSR for BL33 entry 80 ******************************************************************************/ 81 #ifdef __aarch64__ 82 uint32_t arm_get_spsr_for_bl33_entry(void) 83 { 84 unsigned int mode; 85 uint32_t spsr; 86 87 /* Figure out what mode we enter the non-secure world in */ 88 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1; 89 90 /* 91 * TODO: Consider the possibility of specifying the SPSR in 92 * the FIP ToC and allowing the platform to have a say as 93 * well. 94 */ 95 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 96 return spsr; 97 } 98 #else 99 /******************************************************************************* 100 * Gets SPSR for BL33 entry 101 ******************************************************************************/ 102 uint32_t arm_get_spsr_for_bl33_entry(void) 103 { 104 unsigned int hyp_status, mode, spsr; 105 106 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 107 108 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 109 110 /* 111 * TODO: Consider the possibility of specifying the SPSR in 112 * the FIP ToC and allowing the platform to have a say as 113 * well. 114 */ 115 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 116 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 117 return spsr; 118 } 119 #endif /* __aarch64__ */ 120 121 /******************************************************************************* 122 * Configures access to the system counter timer module. 123 ******************************************************************************/ 124 #ifdef ARM_SYS_TIMCTL_BASE 125 void arm_configure_sys_timer(void) 126 { 127 unsigned int reg_val; 128 129 /* Read the frequency of the system counter */ 130 unsigned int freq_val = plat_get_syscnt_freq2(); 131 132 #if ARM_CONFIG_CNTACR 133 reg_val = (1U << CNTACR_RPCT_SHIFT) | (1U << CNTACR_RVCT_SHIFT); 134 reg_val |= (1U << CNTACR_RFRQ_SHIFT) | (1U << CNTACR_RVOFF_SHIFT); 135 reg_val |= (1U << CNTACR_RWVT_SHIFT) | (1U << CNTACR_RWPT_SHIFT); 136 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val); 137 #endif /* ARM_CONFIG_CNTACR */ 138 139 reg_val = (1U << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); 140 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); 141 142 /* 143 * Initialize CNTFRQ register in CNTCTLBase frame. The CNTFRQ 144 * system register initialized during psci_arch_setup() is different 145 * from this and has to be updated independently. 146 */ 147 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val); 148 149 #if defined(PLAT_juno) || defined(PLAT_n1sdp) 150 /* 151 * Initialize CNTFRQ register in Non-secure CNTBase frame. 152 * This is only required for Juno and N1SDP, because they do not 153 * follow ARM ARM in that the value updated in CNTFRQ is not 154 * reflected in CNTBASEN_CNTFRQ. Hence update the value manually. 155 */ 156 mmio_write_32(ARM_SYS_CNT_BASE_NS + CNTBASEN_CNTFRQ, freq_val); 157 #endif 158 } 159 #endif /* ARM_SYS_TIMCTL_BASE */ 160 161 /******************************************************************************* 162 * Returns ARM platform specific memory map regions. 163 ******************************************************************************/ 164 const mmap_region_t *plat_arm_get_mmap(void) 165 { 166 return plat_arm_mmap; 167 } 168 169 #ifdef ARM_SYS_CNTCTL_BASE 170 171 unsigned int plat_get_syscnt_freq2(void) 172 { 173 unsigned int counter_base_frequency; 174 175 /* Read the frequency from Frequency modes table */ 176 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); 177 178 /* The first entry of the frequency modes table must not be 0 */ 179 if (counter_base_frequency == 0U) 180 panic(); 181 182 return counter_base_frequency; 183 } 184 185 #endif /* ARM_SYS_CNTCTL_BASE */ 186 187 #if SDEI_SUPPORT 188 /* 189 * Translate SDEI entry point to PA, and perform standard ARM entry point 190 * validation on it. 191 */ 192 int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode) 193 { 194 uint64_t par, pa; 195 u_register_t scr_el3; 196 197 /* Doing Non-secure address translation requires SCR_EL3.NS set */ 198 scr_el3 = read_scr_el3(); 199 write_scr_el3(scr_el3 | SCR_NS_BIT); 200 isb(); 201 202 assert((client_mode == MODE_EL2) || (client_mode == MODE_EL1)); 203 if (client_mode == MODE_EL2) { 204 /* 205 * Translate entry point to Physical Address using the EL2 206 * translation regime. 207 */ 208 ats1e2r(ep); 209 } else { 210 /* 211 * Translate entry point to Physical Address using the EL1&0 212 * translation regime, including stage 2. 213 */ 214 ats12e1r(ep); 215 } 216 isb(); 217 par = read_par_el1(); 218 219 /* Restore original SCRL_EL3 */ 220 write_scr_el3(scr_el3); 221 isb(); 222 223 /* If the translation resulted in fault, return failure */ 224 if ((par & PAR_F_MASK) != 0) 225 return -1; 226 227 /* Extract Physical Address from PAR */ 228 pa = (par & (PAR_ADDR_MASK << PAR_ADDR_SHIFT)); 229 230 /* Perform NS entry point validation on the physical address */ 231 return arm_validate_ns_entrypoint(pa); 232 } 233 #endif 234