1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #include <arch.h> 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <debug.h> 34 #include <mmio.h> 35 #include <plat_arm.h> 36 #include <platform_def.h> 37 #include <xlat_tables_v2.h> 38 39 extern const mmap_region_t plat_arm_mmap[]; 40 41 /* Weak definitions may be overridden in specific ARM standard platform */ 42 #pragma weak plat_get_ns_image_entrypoint 43 #pragma weak plat_arm_get_mmap 44 45 /* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid 46 * conflicts with the definition in plat/common. */ 47 #if ERROR_DEPRECATED 48 #pragma weak plat_get_syscnt_freq2 49 #endif 50 51 /* 52 * Set up the page tables for the generic and platform-specific memory regions. 53 * The extents of the generic memory regions are specified by the function 54 * arguments and consist of: 55 * - Trusted SRAM seen by the BL image; 56 * - Code section; 57 * - Read-only data section; 58 * - Coherent memory region, if applicable. 59 */ 60 void arm_setup_page_tables(uintptr_t total_base, 61 size_t total_size, 62 uintptr_t code_start, 63 uintptr_t code_limit, 64 uintptr_t rodata_start, 65 uintptr_t rodata_limit 66 #if USE_COHERENT_MEM 67 , 68 uintptr_t coh_start, 69 uintptr_t coh_limit 70 #endif 71 ) 72 { 73 /* 74 * Map the Trusted SRAM with appropriate memory attributes. 75 * Subsequent mappings will adjust the attributes for specific regions. 76 */ 77 VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n", 78 (void *) total_base, (void *) (total_base + total_size)); 79 mmap_add_region(total_base, total_base, 80 total_size, 81 MT_MEMORY | MT_RW | MT_SECURE); 82 83 /* Re-map the code section */ 84 VERBOSE("Code region: %p - %p\n", 85 (void *) code_start, (void *) code_limit); 86 mmap_add_region(code_start, code_start, 87 code_limit - code_start, 88 MT_CODE | MT_SECURE); 89 90 /* Re-map the read-only data section */ 91 VERBOSE("Read-only data region: %p - %p\n", 92 (void *) rodata_start, (void *) rodata_limit); 93 mmap_add_region(rodata_start, rodata_start, 94 rodata_limit - rodata_start, 95 MT_RO_DATA | MT_SECURE); 96 97 #if USE_COHERENT_MEM 98 /* Re-map the coherent memory region */ 99 VERBOSE("Coherent region: %p - %p\n", 100 (void *) coh_start, (void *) coh_limit); 101 mmap_add_region(coh_start, coh_start, 102 coh_limit - coh_start, 103 MT_DEVICE | MT_RW | MT_SECURE); 104 #endif 105 106 /* Now (re-)map the platform-specific memory regions */ 107 mmap_add(plat_arm_get_mmap()); 108 109 /* Create the page tables to reflect the above mappings */ 110 init_xlat_tables(); 111 } 112 113 uintptr_t plat_get_ns_image_entrypoint(void) 114 { 115 #ifdef PRELOADED_BL33_BASE 116 return PRELOADED_BL33_BASE; 117 #else 118 return PLAT_ARM_NS_IMAGE_OFFSET; 119 #endif 120 } 121 122 /******************************************************************************* 123 * Gets SPSR for BL32 entry 124 ******************************************************************************/ 125 uint32_t arm_get_spsr_for_bl32_entry(void) 126 { 127 /* 128 * The Secure Payload Dispatcher service is responsible for 129 * setting the SPSR prior to entry into the BL32 image. 130 */ 131 return 0; 132 } 133 134 /******************************************************************************* 135 * Gets SPSR for BL33 entry 136 ******************************************************************************/ 137 #ifndef AARCH32 138 uint32_t arm_get_spsr_for_bl33_entry(void) 139 { 140 unsigned long el_status; 141 unsigned int mode; 142 uint32_t spsr; 143 144 /* Figure out what mode we enter the non-secure world in */ 145 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 146 el_status &= ID_AA64PFR0_ELX_MASK; 147 148 mode = (el_status) ? MODE_EL2 : MODE_EL1; 149 150 /* 151 * TODO: Consider the possibility of specifying the SPSR in 152 * the FIP ToC and allowing the platform to have a say as 153 * well. 154 */ 155 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 156 return spsr; 157 } 158 #else 159 /******************************************************************************* 160 * Gets SPSR for BL33 entry 161 ******************************************************************************/ 162 uint32_t arm_get_spsr_for_bl33_entry(void) 163 { 164 unsigned int hyp_status, mode, spsr; 165 166 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 167 168 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 169 170 /* 171 * TODO: Consider the possibility of specifying the SPSR in 172 * the FIP ToC and allowing the platform to have a say as 173 * well. 174 */ 175 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 176 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 177 return spsr; 178 } 179 #endif /* AARCH32 */ 180 181 /******************************************************************************* 182 * Configures access to the system counter timer module. 183 ******************************************************************************/ 184 #ifdef ARM_SYS_TIMCTL_BASE 185 void arm_configure_sys_timer(void) 186 { 187 unsigned int reg_val; 188 189 #if ARM_CONFIG_CNTACR 190 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); 191 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); 192 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); 193 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val); 194 #endif /* ARM_CONFIG_CNTACR */ 195 196 reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); 197 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); 198 } 199 #endif /* ARM_SYS_TIMCTL_BASE */ 200 201 /******************************************************************************* 202 * Returns ARM platform specific memory map regions. 203 ******************************************************************************/ 204 const mmap_region_t *plat_arm_get_mmap(void) 205 { 206 return plat_arm_mmap; 207 } 208 209 #ifdef ARM_SYS_CNTCTL_BASE 210 211 unsigned int plat_get_syscnt_freq2(void) 212 { 213 unsigned int counter_base_frequency; 214 215 /* Read the frequency from Frequency modes table */ 216 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); 217 218 /* The first entry of the frequency modes table must not be 0 */ 219 if (counter_base_frequency == 0) 220 panic(); 221 222 return counter_base_frequency; 223 } 224 225 #endif /* ARM_SYS_CNTCTL_BASE */ 226