1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #include <arch.h> 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <debug.h> 34 #include <mmio.h> 35 #include <plat_arm.h> 36 #include <platform_def.h> 37 #include <xlat_tables.h> 38 39 extern const mmap_region_t plat_arm_mmap[]; 40 41 /* Weak definitions may be overridden in specific ARM standard platform */ 42 #pragma weak plat_get_ns_image_entrypoint 43 #pragma weak plat_arm_get_mmap 44 45 /* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid 46 * conflicts with the definition in plat/common. */ 47 #if ERROR_DEPRECATED 48 #pragma weak plat_get_syscnt_freq2 49 #else 50 #pragma weak plat_get_syscnt_freq 51 #endif 52 53 /* 54 * Set up the page tables for the generic and platform-specific memory regions. 55 * The extents of the generic memory regions are specified by the function 56 * arguments and consist of: 57 * - Trusted SRAM seen by the BL image; 58 * - Code section; 59 * - Read-only data section; 60 * - Coherent memory region, if applicable. 61 */ 62 void arm_setup_page_tables(uintptr_t total_base, 63 size_t total_size, 64 uintptr_t code_start, 65 uintptr_t code_limit, 66 uintptr_t rodata_start, 67 uintptr_t rodata_limit 68 #if USE_COHERENT_MEM 69 , 70 uintptr_t coh_start, 71 uintptr_t coh_limit 72 #endif 73 ) 74 { 75 /* 76 * Map the Trusted SRAM with appropriate memory attributes. 77 * Subsequent mappings will adjust the attributes for specific regions. 78 */ 79 VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n", 80 (void *) total_base, (void *) (total_base + total_size)); 81 mmap_add_region(total_base, total_base, 82 total_size, 83 MT_MEMORY | MT_RW | MT_SECURE); 84 85 /* Re-map the code section */ 86 VERBOSE("Code region: %p - %p\n", 87 (void *) code_start, (void *) code_limit); 88 mmap_add_region(code_start, code_start, 89 code_limit - code_start, 90 MT_CODE | MT_SECURE); 91 92 /* Re-map the read-only data section */ 93 VERBOSE("Read-only data region: %p - %p\n", 94 (void *) rodata_start, (void *) rodata_limit); 95 mmap_add_region(rodata_start, rodata_start, 96 rodata_limit - rodata_start, 97 MT_RO_DATA | MT_SECURE); 98 99 #if USE_COHERENT_MEM 100 /* Re-map the coherent memory region */ 101 VERBOSE("Coherent region: %p - %p\n", 102 (void *) coh_start, (void *) coh_limit); 103 mmap_add_region(coh_start, coh_start, 104 coh_limit - coh_start, 105 MT_DEVICE | MT_RW | MT_SECURE); 106 #endif 107 108 /* Now (re-)map the platform-specific memory regions */ 109 mmap_add(plat_arm_get_mmap()); 110 111 /* Create the page tables to reflect the above mappings */ 112 init_xlat_tables(); 113 } 114 115 uintptr_t plat_get_ns_image_entrypoint(void) 116 { 117 #ifdef PRELOADED_BL33_BASE 118 return PRELOADED_BL33_BASE; 119 #else 120 return PLAT_ARM_NS_IMAGE_OFFSET; 121 #endif 122 } 123 124 /******************************************************************************* 125 * Gets SPSR for BL32 entry 126 ******************************************************************************/ 127 uint32_t arm_get_spsr_for_bl32_entry(void) 128 { 129 /* 130 * The Secure Payload Dispatcher service is responsible for 131 * setting the SPSR prior to entry into the BL32 image. 132 */ 133 return 0; 134 } 135 136 /******************************************************************************* 137 * Gets SPSR for BL33 entry 138 ******************************************************************************/ 139 uint32_t arm_get_spsr_for_bl33_entry(void) 140 { 141 unsigned long el_status; 142 unsigned int mode; 143 uint32_t spsr; 144 145 /* Figure out what mode we enter the non-secure world in */ 146 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 147 el_status &= ID_AA64PFR0_ELX_MASK; 148 149 mode = (el_status) ? MODE_EL2 : MODE_EL1; 150 151 /* 152 * TODO: Consider the possibility of specifying the SPSR in 153 * the FIP ToC and allowing the platform to have a say as 154 * well. 155 */ 156 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 157 return spsr; 158 } 159 160 /******************************************************************************* 161 * Configures access to the system counter timer module. 162 ******************************************************************************/ 163 #ifdef ARM_SYS_TIMCTL_BASE 164 void arm_configure_sys_timer(void) 165 { 166 unsigned int reg_val; 167 168 #if ARM_CONFIG_CNTACR 169 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); 170 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); 171 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); 172 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val); 173 #endif /* ARM_CONFIG_CNTACR */ 174 175 reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); 176 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); 177 } 178 #endif /* ARM_SYS_TIMCTL_BASE */ 179 180 /******************************************************************************* 181 * Returns ARM platform specific memory map regions. 182 ******************************************************************************/ 183 const mmap_region_t *plat_arm_get_mmap(void) 184 { 185 return plat_arm_mmap; 186 } 187 188 #ifdef ARM_SYS_CNTCTL_BASE 189 190 #if ERROR_DEPRECATED 191 unsigned int plat_get_syscnt_freq2(void) 192 { 193 unsigned int counter_base_frequency; 194 #else 195 unsigned long long plat_get_syscnt_freq(void) 196 { 197 unsigned long long counter_base_frequency; 198 #endif /* ERROR_DEPRECATED */ 199 200 /* Read the frequency from Frequency modes table */ 201 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); 202 203 /* The first entry of the frequency modes table must not be 0 */ 204 if (counter_base_frequency == 0) 205 panic(); 206 207 return counter_base_frequency; 208 } 209 210 #endif /* ARM_SYS_CNTCTL_BASE */ 211