1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <common/romlib.h> 15 #include <lib/mmio.h> 16 #include <lib/xlat_tables/xlat_tables_compat.h> 17 #include <plat/arm/common/plat_arm.h> 18 #include <plat/common/platform.h> 19 20 /* Weak definitions may be overridden in specific ARM standard platform */ 21 #pragma weak plat_get_ns_image_entrypoint 22 #pragma weak plat_arm_get_mmap 23 24 /* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid 25 * conflicts with the definition in plat/common. */ 26 #pragma weak plat_get_syscnt_freq2 27 28 /* Get ARM SOC-ID */ 29 #pragma weak plat_arm_get_soc_id 30 31 /******************************************************************************* 32 * Changes the memory attributes for the region of mapped memory where the BL 33 * image's translation tables are located such that the tables will have 34 * read-only permissions. 35 ******************************************************************************/ 36 #if PLAT_RO_XLAT_TABLES 37 void arm_xlat_make_tables_readonly(void) 38 { 39 int rc = xlat_make_tables_readonly(); 40 41 if (rc != 0) { 42 ERROR("Failed to make translation tables read-only at EL%u.\n", 43 get_current_el()); 44 panic(); 45 } 46 47 INFO("Translation tables are now read-only at EL%u.\n", 48 get_current_el()); 49 } 50 #endif 51 52 void arm_setup_romlib(void) 53 { 54 #if USE_ROMLIB 55 if (!rom_lib_init(ROMLIB_VERSION)) 56 panic(); 57 #endif 58 } 59 60 uintptr_t plat_get_ns_image_entrypoint(void) 61 { 62 #ifdef PRELOADED_BL33_BASE 63 return PRELOADED_BL33_BASE; 64 #else 65 return PLAT_ARM_NS_IMAGE_BASE; 66 #endif 67 } 68 69 /******************************************************************************* 70 * Gets SPSR for BL32 entry 71 ******************************************************************************/ 72 uint32_t arm_get_spsr_for_bl32_entry(void) 73 { 74 /* 75 * The Secure Payload Dispatcher service is responsible for 76 * setting the SPSR prior to entry into the BL32 image. 77 */ 78 return 0; 79 } 80 81 /******************************************************************************* 82 * Gets SPSR for BL33 entry 83 ******************************************************************************/ 84 #ifdef __aarch64__ 85 uint32_t arm_get_spsr_for_bl33_entry(void) 86 { 87 unsigned int mode; 88 uint32_t spsr; 89 90 /* Figure out what mode we enter the non-secure world in */ 91 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1; 92 93 /* 94 * TODO: Consider the possibility of specifying the SPSR in 95 * the FIP ToC and allowing the platform to have a say as 96 * well. 97 */ 98 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 99 return spsr; 100 } 101 #else 102 /******************************************************************************* 103 * Gets SPSR for BL33 entry 104 ******************************************************************************/ 105 uint32_t arm_get_spsr_for_bl33_entry(void) 106 { 107 unsigned int hyp_status, mode, spsr; 108 109 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 110 111 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 112 113 /* 114 * TODO: Consider the possibility of specifying the SPSR in 115 * the FIP ToC and allowing the platform to have a say as 116 * well. 117 */ 118 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 119 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 120 return spsr; 121 } 122 #endif /* __aarch64__ */ 123 124 /******************************************************************************* 125 * Configures access to the system counter timer module. 126 ******************************************************************************/ 127 #ifdef ARM_SYS_TIMCTL_BASE 128 void arm_configure_sys_timer(void) 129 { 130 unsigned int reg_val; 131 132 /* Read the frequency of the system counter */ 133 unsigned int freq_val = plat_get_syscnt_freq2(); 134 135 #if ARM_CONFIG_CNTACR 136 reg_val = (1U << CNTACR_RPCT_SHIFT) | (1U << CNTACR_RVCT_SHIFT); 137 reg_val |= (1U << CNTACR_RFRQ_SHIFT) | (1U << CNTACR_RVOFF_SHIFT); 138 reg_val |= (1U << CNTACR_RWVT_SHIFT) | (1U << CNTACR_RWPT_SHIFT); 139 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val); 140 #endif /* ARM_CONFIG_CNTACR */ 141 142 reg_val = (1U << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); 143 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); 144 145 /* 146 * Initialize CNTFRQ register in CNTCTLBase frame. The CNTFRQ 147 * system register initialized during psci_arch_setup() is different 148 * from this and has to be updated independently. 149 */ 150 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val); 151 152 #if defined(PLAT_juno) || defined(PLAT_n1sdp) 153 /* 154 * Initialize CNTFRQ register in Non-secure CNTBase frame. 155 * This is only required for Juno and N1SDP, because they do not 156 * follow ARM ARM in that the value updated in CNTFRQ is not 157 * reflected in CNTBASEN_CNTFRQ. Hence update the value manually. 158 */ 159 mmio_write_32(ARM_SYS_CNT_BASE_NS + CNTBASEN_CNTFRQ, freq_val); 160 #endif 161 } 162 #endif /* ARM_SYS_TIMCTL_BASE */ 163 164 /******************************************************************************* 165 * Returns ARM platform specific memory map regions. 166 ******************************************************************************/ 167 const mmap_region_t *plat_arm_get_mmap(void) 168 { 169 return plat_arm_mmap; 170 } 171 172 #ifdef ARM_SYS_CNTCTL_BASE 173 174 unsigned int plat_get_syscnt_freq2(void) 175 { 176 unsigned int counter_base_frequency; 177 178 /* Read the frequency from Frequency modes table */ 179 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); 180 181 /* The first entry of the frequency modes table must not be 0 */ 182 if (counter_base_frequency == 0U) 183 panic(); 184 185 return counter_base_frequency; 186 } 187 188 #endif /* ARM_SYS_CNTCTL_BASE */ 189 190 #if SDEI_SUPPORT 191 /* 192 * Translate SDEI entry point to PA, and perform standard ARM entry point 193 * validation on it. 194 */ 195 int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode) 196 { 197 uint64_t par, pa; 198 u_register_t scr_el3; 199 200 /* Doing Non-secure address translation requires SCR_EL3.NS set */ 201 scr_el3 = read_scr_el3(); 202 write_scr_el3(scr_el3 | SCR_NS_BIT); 203 isb(); 204 205 assert((client_mode == MODE_EL2) || (client_mode == MODE_EL1)); 206 if (client_mode == MODE_EL2) { 207 /* 208 * Translate entry point to Physical Address using the EL2 209 * translation regime. 210 */ 211 ats1e2r(ep); 212 } else { 213 /* 214 * Translate entry point to Physical Address using the EL1&0 215 * translation regime, including stage 2. 216 */ 217 ats12e1r(ep); 218 } 219 isb(); 220 par = read_par_el1(); 221 222 /* Restore original SCRL_EL3 */ 223 write_scr_el3(scr_el3); 224 isb(); 225 226 /* If the translation resulted in fault, return failure */ 227 if ((par & PAR_F_MASK) != 0) 228 return -1; 229 230 /* Extract Physical Address from PAR */ 231 pa = (par & (PAR_ADDR_MASK << PAR_ADDR_SHIFT)); 232 233 /* Perform NS entry point validation on the physical address */ 234 return arm_validate_ns_entrypoint(pa); 235 } 236 #endif 237 238 /* 239 * Weak function to get ARM platform SOC-ID, Always return SOC-ID=0 240 * ToDo: Get proper SOC-ID for every ARM platform and define this 241 * function separately for every ARM platform. 242 */ 243 uint32_t plat_arm_get_soc_id(void) 244 { 245 return 0U; 246 } 247 248 /* Get SOC version */ 249 int32_t plat_get_soc_version(void) 250 { 251 return (int32_t) 252 ((ARM_SOC_IDENTIFICATION_CODE << ARM_SOC_IDENTIFICATION_SHIFT) 253 | (ARM_SOC_CONTINUATION_CODE << ARM_SOC_CONTINUATION_SHIFT) 254 | plat_arm_get_soc_id()); 255 } 256