1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <arch.h> 7 #include <arch_helpers.h> 8 #include <arm_xlat_tables.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <mmio.h> 12 #include <plat_arm.h> 13 #include <platform.h> 14 #include <platform_def.h> 15 #include <romlib.h> 16 #include <secure_partition.h> 17 18 /* Weak definitions may be overridden in specific ARM standard platform */ 19 #pragma weak plat_get_ns_image_entrypoint 20 #pragma weak plat_arm_get_mmap 21 22 /* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid 23 * conflicts with the definition in plat/common. */ 24 #pragma weak plat_get_syscnt_freq2 25 26 27 void arm_setup_romlib(void) 28 { 29 #if USE_ROMLIB 30 if (!rom_lib_init(ROMLIB_VERSION)) 31 panic(); 32 #endif 33 } 34 35 /* 36 * Set up the page tables for the generic and platform-specific memory regions. 37 * The size of the Trusted SRAM seen by the BL image must be specified as well 38 * as an array specifying the generic memory regions which can be; 39 * - Code section; 40 * - Read-only data section; 41 * - Coherent memory region, if applicable. 42 */ 43 44 void arm_setup_page_tables(const mmap_region_t bl_regions[], 45 const mmap_region_t plat_regions[]) 46 { 47 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE 48 const mmap_region_t *regions = bl_regions; 49 50 while (regions->size != 0U) { 51 VERBOSE("Region: 0x%lx - 0x%lx has attributes 0x%x\n", 52 regions->base_va, 53 (regions->base_va + regions->size), 54 regions->attr); 55 regions++; 56 } 57 #endif 58 /* 59 * Map the Trusted SRAM with appropriate memory attributes. 60 * Subsequent mappings will adjust the attributes for specific regions. 61 */ 62 mmap_add(bl_regions); 63 /* Now (re-)map the platform-specific memory regions */ 64 mmap_add(plat_regions); 65 66 /* Create the page tables to reflect the above mappings */ 67 init_xlat_tables(); 68 } 69 70 uintptr_t plat_get_ns_image_entrypoint(void) 71 { 72 #ifdef PRELOADED_BL33_BASE 73 return PRELOADED_BL33_BASE; 74 #else 75 return PLAT_ARM_NS_IMAGE_OFFSET; 76 #endif 77 } 78 79 /******************************************************************************* 80 * Gets SPSR for BL32 entry 81 ******************************************************************************/ 82 uint32_t arm_get_spsr_for_bl32_entry(void) 83 { 84 /* 85 * The Secure Payload Dispatcher service is responsible for 86 * setting the SPSR prior to entry into the BL32 image. 87 */ 88 return 0; 89 } 90 91 /******************************************************************************* 92 * Gets SPSR for BL33 entry 93 ******************************************************************************/ 94 #ifndef AARCH32 95 uint32_t arm_get_spsr_for_bl33_entry(void) 96 { 97 unsigned int mode; 98 uint32_t spsr; 99 100 /* Figure out what mode we enter the non-secure world in */ 101 mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1; 102 103 /* 104 * TODO: Consider the possibility of specifying the SPSR in 105 * the FIP ToC and allowing the platform to have a say as 106 * well. 107 */ 108 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 109 return spsr; 110 } 111 #else 112 /******************************************************************************* 113 * Gets SPSR for BL33 entry 114 ******************************************************************************/ 115 uint32_t arm_get_spsr_for_bl33_entry(void) 116 { 117 unsigned int hyp_status, mode, spsr; 118 119 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 120 121 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 122 123 /* 124 * TODO: Consider the possibility of specifying the SPSR in 125 * the FIP ToC and allowing the platform to have a say as 126 * well. 127 */ 128 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 129 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 130 return spsr; 131 } 132 #endif /* AARCH32 */ 133 134 /******************************************************************************* 135 * Configures access to the system counter timer module. 136 ******************************************************************************/ 137 #ifdef ARM_SYS_TIMCTL_BASE 138 void arm_configure_sys_timer(void) 139 { 140 unsigned int reg_val; 141 142 /* Read the frequency of the system counter */ 143 unsigned int freq_val = plat_get_syscnt_freq2(); 144 145 #if ARM_CONFIG_CNTACR 146 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); 147 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); 148 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); 149 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val); 150 #endif /* ARM_CONFIG_CNTACR */ 151 152 reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); 153 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); 154 155 /* 156 * Initialize CNTFRQ register in CNTCTLBase frame. The CNTFRQ 157 * system register initialized during psci_arch_setup() is different 158 * from this and has to be updated independently. 159 */ 160 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val); 161 162 #ifdef PLAT_juno 163 /* 164 * Initialize CNTFRQ register in Non-secure CNTBase frame. 165 * This is only required for Juno, because it doesn't follow ARM ARM 166 * in that the value updated in CNTFRQ is not reflected in CNTBASE_CNTFRQ. 167 * Hence update the value manually. 168 */ 169 mmio_write_32(ARM_SYS_CNT_BASE_NS + CNTBASE_CNTFRQ, freq_val); 170 #endif 171 } 172 #endif /* ARM_SYS_TIMCTL_BASE */ 173 174 /******************************************************************************* 175 * Returns ARM platform specific memory map regions. 176 ******************************************************************************/ 177 const mmap_region_t *plat_arm_get_mmap(void) 178 { 179 return plat_arm_mmap; 180 } 181 182 #ifdef ARM_SYS_CNTCTL_BASE 183 184 unsigned int plat_get_syscnt_freq2(void) 185 { 186 unsigned int counter_base_frequency; 187 188 /* Read the frequency from Frequency modes table */ 189 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); 190 191 /* The first entry of the frequency modes table must not be 0 */ 192 if (counter_base_frequency == 0) 193 panic(); 194 195 return counter_base_frequency; 196 } 197 198 #endif /* ARM_SYS_CNTCTL_BASE */ 199 200 #if SDEI_SUPPORT 201 /* 202 * Translate SDEI entry point to PA, and perform standard ARM entry point 203 * validation on it. 204 */ 205 int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode) 206 { 207 uint64_t par, pa; 208 uint32_t scr_el3; 209 210 /* Doing Non-secure address translation requires SCR_EL3.NS set */ 211 scr_el3 = read_scr_el3(); 212 write_scr_el3(scr_el3 | SCR_NS_BIT); 213 isb(); 214 215 assert((client_mode == MODE_EL2) || (client_mode == MODE_EL1)); 216 if (client_mode == MODE_EL2) { 217 /* 218 * Translate entry point to Physical Address using the EL2 219 * translation regime. 220 */ 221 ats1e2r(ep); 222 } else { 223 /* 224 * Translate entry point to Physical Address using the EL1&0 225 * translation regime, including stage 2. 226 */ 227 ats12e1r(ep); 228 } 229 isb(); 230 par = read_par_el1(); 231 232 /* Restore original SCRL_EL3 */ 233 write_scr_el3(scr_el3); 234 isb(); 235 236 /* If the translation resulted in fault, return failure */ 237 if ((par & PAR_F_MASK) != 0) 238 return -1; 239 240 /* Extract Physical Address from PAR */ 241 pa = (par & (PAR_ADDR_MASK << PAR_ADDR_SHIFT)); 242 243 /* Perform NS entry point validation on the physical address */ 244 return arm_validate_ns_entrypoint(pa); 245 } 246 #endif 247