1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <arch.h> 7 #include <arch_helpers.h> 8 #include <arm_xlat_tables.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <mmio.h> 12 #include <plat_arm.h> 13 #include <platform.h> 14 #include <platform_def.h> 15 #include <romlib.h> 16 #include <secure_partition.h> 17 18 /* Weak definitions may be overridden in specific ARM standard platform */ 19 #pragma weak plat_get_ns_image_entrypoint 20 #pragma weak plat_arm_get_mmap 21 22 /* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid 23 * conflicts with the definition in plat/common. */ 24 #pragma weak plat_get_syscnt_freq2 25 26 27 void arm_setup_romlib(void) 28 { 29 #if USE_ROMLIB 30 if (!rom_lib_init(ROMLIB_VERSION)) 31 panic(); 32 #endif 33 } 34 35 /* 36 * Set up the page tables for the generic and platform-specific memory regions. 37 * The size of the Trusted SRAM seen by the BL image must be specified as well 38 * as an array specifying the generic memory regions which can be; 39 * - Code section; 40 * - Read-only data section; 41 * - Init code section, if applicable 42 * - Coherent memory region, if applicable. 43 */ 44 45 void __init arm_setup_page_tables(const mmap_region_t bl_regions[], 46 const mmap_region_t plat_regions[]) 47 { 48 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE 49 const mmap_region_t *regions = bl_regions; 50 51 while (regions->size != 0U) { 52 VERBOSE("Region: 0x%lx - 0x%lx has attributes 0x%x\n", 53 regions->base_va, 54 (regions->base_va + regions->size), 55 regions->attr); 56 regions++; 57 } 58 #endif 59 /* 60 * Map the Trusted SRAM with appropriate memory attributes. 61 * Subsequent mappings will adjust the attributes for specific regions. 62 */ 63 mmap_add(bl_regions); 64 /* Now (re-)map the platform-specific memory regions */ 65 mmap_add(plat_regions); 66 67 /* Create the page tables to reflect the above mappings */ 68 init_xlat_tables(); 69 } 70 71 uintptr_t plat_get_ns_image_entrypoint(void) 72 { 73 #ifdef PRELOADED_BL33_BASE 74 return PRELOADED_BL33_BASE; 75 #else 76 return PLAT_ARM_NS_IMAGE_OFFSET; 77 #endif 78 } 79 80 /******************************************************************************* 81 * Gets SPSR for BL32 entry 82 ******************************************************************************/ 83 uint32_t arm_get_spsr_for_bl32_entry(void) 84 { 85 /* 86 * The Secure Payload Dispatcher service is responsible for 87 * setting the SPSR prior to entry into the BL32 image. 88 */ 89 return 0; 90 } 91 92 /******************************************************************************* 93 * Gets SPSR for BL33 entry 94 ******************************************************************************/ 95 #ifndef AARCH32 96 uint32_t arm_get_spsr_for_bl33_entry(void) 97 { 98 unsigned int mode; 99 uint32_t spsr; 100 101 /* Figure out what mode we enter the non-secure world in */ 102 mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1; 103 104 /* 105 * TODO: Consider the possibility of specifying the SPSR in 106 * the FIP ToC and allowing the platform to have a say as 107 * well. 108 */ 109 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 110 return spsr; 111 } 112 #else 113 /******************************************************************************* 114 * Gets SPSR for BL33 entry 115 ******************************************************************************/ 116 uint32_t arm_get_spsr_for_bl33_entry(void) 117 { 118 unsigned int hyp_status, mode, spsr; 119 120 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 121 122 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 123 124 /* 125 * TODO: Consider the possibility of specifying the SPSR in 126 * the FIP ToC and allowing the platform to have a say as 127 * well. 128 */ 129 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 130 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 131 return spsr; 132 } 133 #endif /* AARCH32 */ 134 135 /******************************************************************************* 136 * Configures access to the system counter timer module. 137 ******************************************************************************/ 138 #ifdef ARM_SYS_TIMCTL_BASE 139 void arm_configure_sys_timer(void) 140 { 141 unsigned int reg_val; 142 143 /* Read the frequency of the system counter */ 144 unsigned int freq_val = plat_get_syscnt_freq2(); 145 146 #if ARM_CONFIG_CNTACR 147 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); 148 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); 149 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); 150 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val); 151 #endif /* ARM_CONFIG_CNTACR */ 152 153 reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); 154 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); 155 156 /* 157 * Initialize CNTFRQ register in CNTCTLBase frame. The CNTFRQ 158 * system register initialized during psci_arch_setup() is different 159 * from this and has to be updated independently. 160 */ 161 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val); 162 163 #ifdef PLAT_juno 164 /* 165 * Initialize CNTFRQ register in Non-secure CNTBase frame. 166 * This is only required for Juno, because it doesn't follow ARM ARM 167 * in that the value updated in CNTFRQ is not reflected in CNTBASE_CNTFRQ. 168 * Hence update the value manually. 169 */ 170 mmio_write_32(ARM_SYS_CNT_BASE_NS + CNTBASE_CNTFRQ, freq_val); 171 #endif 172 } 173 #endif /* ARM_SYS_TIMCTL_BASE */ 174 175 /******************************************************************************* 176 * Returns ARM platform specific memory map regions. 177 ******************************************************************************/ 178 const mmap_region_t *plat_arm_get_mmap(void) 179 { 180 return plat_arm_mmap; 181 } 182 183 #ifdef ARM_SYS_CNTCTL_BASE 184 185 unsigned int plat_get_syscnt_freq2(void) 186 { 187 unsigned int counter_base_frequency; 188 189 /* Read the frequency from Frequency modes table */ 190 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); 191 192 /* The first entry of the frequency modes table must not be 0 */ 193 if (counter_base_frequency == 0) 194 panic(); 195 196 return counter_base_frequency; 197 } 198 199 #endif /* ARM_SYS_CNTCTL_BASE */ 200 201 #if SDEI_SUPPORT 202 /* 203 * Translate SDEI entry point to PA, and perform standard ARM entry point 204 * validation on it. 205 */ 206 int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode) 207 { 208 uint64_t par, pa; 209 uint32_t scr_el3; 210 211 /* Doing Non-secure address translation requires SCR_EL3.NS set */ 212 scr_el3 = read_scr_el3(); 213 write_scr_el3(scr_el3 | SCR_NS_BIT); 214 isb(); 215 216 assert((client_mode == MODE_EL2) || (client_mode == MODE_EL1)); 217 if (client_mode == MODE_EL2) { 218 /* 219 * Translate entry point to Physical Address using the EL2 220 * translation regime. 221 */ 222 ats1e2r(ep); 223 } else { 224 /* 225 * Translate entry point to Physical Address using the EL1&0 226 * translation regime, including stage 2. 227 */ 228 ats12e1r(ep); 229 } 230 isb(); 231 par = read_par_el1(); 232 233 /* Restore original SCRL_EL3 */ 234 write_scr_el3(scr_el3); 235 isb(); 236 237 /* If the translation resulted in fault, return failure */ 238 if ((par & PAR_F_MASK) != 0) 239 return -1; 240 241 /* Extract Physical Address from PAR */ 242 pa = (par & (PAR_ADDR_MASK << PAR_ADDR_SHIFT)); 243 244 /* Perform NS entry point validation on the physical address */ 245 return arm_validate_ns_entrypoint(pa); 246 } 247 #endif 248