1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <arch.h> 7 #include <arch_helpers.h> 8 #include <arm_xlat_tables.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <mmio.h> 12 #include <plat_arm.h> 13 #include <platform.h> 14 #include <platform_def.h> 15 #include <romlib.h> 16 #include <secure_partition.h> 17 18 /* Weak definitions may be overridden in specific ARM standard platform */ 19 #pragma weak plat_get_ns_image_entrypoint 20 #pragma weak plat_arm_get_mmap 21 22 /* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid 23 * conflicts with the definition in plat/common. */ 24 #if ERROR_DEPRECATED 25 #pragma weak plat_get_syscnt_freq2 26 #endif 27 28 29 void arm_setup_romlib(void) 30 { 31 #if USE_ROMLIB 32 if (!rom_lib_init(ROMLIB_VERSION)) 33 panic(); 34 #endif 35 } 36 37 /* 38 * Set up the page tables for the generic and platform-specific memory regions. 39 * The size of the Trusted SRAM seen by the BL image must be specified as well 40 * as an array specifying the generic memory regions which can be; 41 * - Code section; 42 * - Read-only data section; 43 * - Coherent memory region, if applicable. 44 */ 45 46 void arm_setup_page_tables(const mmap_region_t bl_regions[], 47 const mmap_region_t plat_regions[]) 48 { 49 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE 50 const mmap_region_t *regions = bl_regions; 51 52 while (regions->size != 0U) { 53 VERBOSE("Region: 0x%lx - 0x%lx has attributes 0x%x\n", 54 regions->base_va, 55 (regions->base_va + regions->size), 56 regions->attr); 57 regions++; 58 } 59 #endif 60 /* 61 * Map the Trusted SRAM with appropriate memory attributes. 62 * Subsequent mappings will adjust the attributes for specific regions. 63 */ 64 mmap_add(bl_regions); 65 /* Now (re-)map the platform-specific memory regions */ 66 mmap_add(plat_regions); 67 68 /* Create the page tables to reflect the above mappings */ 69 init_xlat_tables(); 70 } 71 72 uintptr_t plat_get_ns_image_entrypoint(void) 73 { 74 #ifdef PRELOADED_BL33_BASE 75 return PRELOADED_BL33_BASE; 76 #else 77 return PLAT_ARM_NS_IMAGE_OFFSET; 78 #endif 79 } 80 81 /******************************************************************************* 82 * Gets SPSR for BL32 entry 83 ******************************************************************************/ 84 uint32_t arm_get_spsr_for_bl32_entry(void) 85 { 86 /* 87 * The Secure Payload Dispatcher service is responsible for 88 * setting the SPSR prior to entry into the BL32 image. 89 */ 90 return 0; 91 } 92 93 /******************************************************************************* 94 * Gets SPSR for BL33 entry 95 ******************************************************************************/ 96 #ifndef AARCH32 97 uint32_t arm_get_spsr_for_bl33_entry(void) 98 { 99 unsigned int mode; 100 uint32_t spsr; 101 102 /* Figure out what mode we enter the non-secure world in */ 103 mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1; 104 105 /* 106 * TODO: Consider the possibility of specifying the SPSR in 107 * the FIP ToC and allowing the platform to have a say as 108 * well. 109 */ 110 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 111 return spsr; 112 } 113 #else 114 /******************************************************************************* 115 * Gets SPSR for BL33 entry 116 ******************************************************************************/ 117 uint32_t arm_get_spsr_for_bl33_entry(void) 118 { 119 unsigned int hyp_status, mode, spsr; 120 121 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 122 123 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 124 125 /* 126 * TODO: Consider the possibility of specifying the SPSR in 127 * the FIP ToC and allowing the platform to have a say as 128 * well. 129 */ 130 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 131 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 132 return spsr; 133 } 134 #endif /* AARCH32 */ 135 136 /******************************************************************************* 137 * Configures access to the system counter timer module. 138 ******************************************************************************/ 139 #ifdef ARM_SYS_TIMCTL_BASE 140 void arm_configure_sys_timer(void) 141 { 142 unsigned int reg_val; 143 144 /* Read the frequency of the system counter */ 145 unsigned int freq_val = plat_get_syscnt_freq2(); 146 147 #if ARM_CONFIG_CNTACR 148 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); 149 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); 150 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); 151 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val); 152 #endif /* ARM_CONFIG_CNTACR */ 153 154 reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); 155 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); 156 157 /* 158 * Initialize CNTFRQ register in CNTCTLBase frame. The CNTFRQ 159 * system register initialized during psci_arch_setup() is different 160 * from this and has to be updated independently. 161 */ 162 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val); 163 164 #ifdef PLAT_juno 165 /* 166 * Initialize CNTFRQ register in Non-secure CNTBase frame. 167 * This is only required for Juno, because it doesn't follow ARM ARM 168 * in that the value updated in CNTFRQ is not reflected in CNTBASE_CNTFRQ. 169 * Hence update the value manually. 170 */ 171 mmio_write_32(ARM_SYS_CNT_BASE_NS + CNTBASE_CNTFRQ, freq_val); 172 #endif 173 } 174 #endif /* ARM_SYS_TIMCTL_BASE */ 175 176 /******************************************************************************* 177 * Returns ARM platform specific memory map regions. 178 ******************************************************************************/ 179 const mmap_region_t *plat_arm_get_mmap(void) 180 { 181 return plat_arm_mmap; 182 } 183 184 #ifdef ARM_SYS_CNTCTL_BASE 185 186 unsigned int plat_get_syscnt_freq2(void) 187 { 188 unsigned int counter_base_frequency; 189 190 /* Read the frequency from Frequency modes table */ 191 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); 192 193 /* The first entry of the frequency modes table must not be 0 */ 194 if (counter_base_frequency == 0) 195 panic(); 196 197 return counter_base_frequency; 198 } 199 200 #endif /* ARM_SYS_CNTCTL_BASE */ 201 202 #if SDEI_SUPPORT 203 /* 204 * Translate SDEI entry point to PA, and perform standard ARM entry point 205 * validation on it. 206 */ 207 int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode) 208 { 209 uint64_t par, pa; 210 uint32_t scr_el3; 211 212 /* Doing Non-secure address translation requires SCR_EL3.NS set */ 213 scr_el3 = read_scr_el3(); 214 write_scr_el3(scr_el3 | SCR_NS_BIT); 215 isb(); 216 217 assert((client_mode == MODE_EL2) || (client_mode == MODE_EL1)); 218 if (client_mode == MODE_EL2) { 219 /* 220 * Translate entry point to Physical Address using the EL2 221 * translation regime. 222 */ 223 ats1e2r(ep); 224 } else { 225 /* 226 * Translate entry point to Physical Address using the EL1&0 227 * translation regime, including stage 2. 228 */ 229 ats12e1r(ep); 230 } 231 isb(); 232 par = read_par_el1(); 233 234 /* Restore original SCRL_EL3 */ 235 write_scr_el3(scr_el3); 236 isb(); 237 238 /* If the translation resulted in fault, return failure */ 239 if ((par & PAR_F_MASK) != 0) 240 return -1; 241 242 /* Extract Physical Address from PAR */ 243 pa = (par & (PAR_ADDR_MASK << PAR_ADDR_SHIFT)); 244 245 /* Perform NS entry point validation on the physical address */ 246 return arm_validate_ns_entrypoint(pa); 247 } 248 #endif 249