1 /* 2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <drivers/console.h> 14 #include <lib/debugfs.h> 15 #include <lib/extensions/ras.h> 16 #include <lib/gpt_rme/gpt_rme.h> 17 #include <lib/mmio.h> 18 #include <lib/xlat_tables/xlat_tables_compat.h> 19 #include <plat/arm/common/plat_arm.h> 20 #include <plat/common/platform.h> 21 #include <platform_def.h> 22 23 /* 24 * Placeholder variables for copying the arguments that have been passed to 25 * BL31 from BL2. 26 */ 27 static entry_point_info_t bl32_image_ep_info; 28 static entry_point_info_t bl33_image_ep_info; 29 #if ENABLE_RME 30 static entry_point_info_t rmm_image_ep_info; 31 #endif 32 33 #if !RESET_TO_BL31 34 /* 35 * Check that BL31_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page 36 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. 37 */ 38 CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows); 39 #endif 40 41 /* Weak definitions may be overridden in specific ARM standard platform */ 42 #pragma weak bl31_early_platform_setup2 43 #pragma weak bl31_platform_setup 44 #pragma weak bl31_plat_arch_setup 45 #pragma weak bl31_plat_get_next_image_ep_info 46 47 #define MAP_BL31_TOTAL MAP_REGION_FLAT( \ 48 BL31_START, \ 49 BL31_END - BL31_START, \ 50 MT_MEMORY | MT_RW | EL3_PAS) 51 #if RECLAIM_INIT_CODE 52 IMPORT_SYM(unsigned long, __INIT_CODE_START__, BL_INIT_CODE_BASE); 53 IMPORT_SYM(unsigned long, __INIT_CODE_END__, BL_CODE_END_UNALIGNED); 54 IMPORT_SYM(unsigned long, __STACKS_END__, BL_STACKS_END_UNALIGNED); 55 56 #define BL_INIT_CODE_END ((BL_CODE_END_UNALIGNED + PAGE_SIZE - 1) & \ 57 ~(PAGE_SIZE - 1)) 58 #define BL_STACKS_END ((BL_STACKS_END_UNALIGNED + PAGE_SIZE - 1) & \ 59 ~(PAGE_SIZE - 1)) 60 61 #define MAP_BL_INIT_CODE MAP_REGION_FLAT( \ 62 BL_INIT_CODE_BASE, \ 63 BL_INIT_CODE_END \ 64 - BL_INIT_CODE_BASE, \ 65 MT_CODE | EL3_PAS) 66 #endif 67 68 #if SEPARATE_NOBITS_REGION 69 #define MAP_BL31_NOBITS MAP_REGION_FLAT( \ 70 BL31_NOBITS_BASE, \ 71 BL31_NOBITS_LIMIT \ 72 - BL31_NOBITS_BASE, \ 73 MT_MEMORY | MT_RW | EL3_PAS) 74 75 #endif 76 /******************************************************************************* 77 * Return a pointer to the 'entry_point_info' structure of the next image for the 78 * security state specified. BL33 corresponds to the non-secure image type 79 * while BL32 corresponds to the secure image type. A NULL pointer is returned 80 * if the image does not exist. 81 ******************************************************************************/ 82 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 83 { 84 entry_point_info_t *next_image_info; 85 86 assert(sec_state_is_valid(type)); 87 if (type == NON_SECURE) { 88 next_image_info = &bl33_image_ep_info; 89 } 90 #if ENABLE_RME 91 else if (type == REALM) { 92 next_image_info = &rmm_image_ep_info; 93 } 94 #endif 95 else { 96 next_image_info = &bl32_image_ep_info; 97 } 98 99 /* 100 * None of the images on the ARM development platforms can have 0x0 101 * as the entrypoint 102 */ 103 if (next_image_info->pc) 104 return next_image_info; 105 else 106 return NULL; 107 } 108 109 /******************************************************************************* 110 * Perform any BL31 early platform setup common to ARM standard platforms. 111 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 112 * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be 113 * done before the MMU is initialized so that the memory layout can be used 114 * while creating page tables. BL2 has flushed this information to memory, so 115 * we are guaranteed to pick up good data. 116 ******************************************************************************/ 117 void __init arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 118 uintptr_t hw_config, void *plat_params_from_bl2) 119 { 120 /* Initialize the console to provide early debug support */ 121 arm_console_boot_init(); 122 123 #if RESET_TO_BL31 124 /* There are no parameters from BL2 if BL31 is a reset vector */ 125 assert(from_bl2 == NULL); 126 assert(plat_params_from_bl2 == NULL); 127 128 # ifdef BL32_BASE 129 /* Populate entry point information for BL32 */ 130 SET_PARAM_HEAD(&bl32_image_ep_info, 131 PARAM_EP, 132 VERSION_1, 133 0); 134 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 135 bl32_image_ep_info.pc = BL32_BASE; 136 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 137 138 #if defined(SPD_spmd) 139 /* SPM (hafnium in secure world) expects SPM Core manifest base address 140 * in x0, which in !RESET_TO_BL31 case loaded after base of non shared 141 * SRAM(after 4KB offset of SRAM). But in RESET_TO_BL31 case all non 142 * shared SRAM is allocated to BL31, so to avoid overwriting of manifest 143 * keep it in the last page. 144 */ 145 bl32_image_ep_info.args.arg0 = ARM_TRUSTED_SRAM_BASE + 146 PLAT_ARM_TRUSTED_SRAM_SIZE - PAGE_SIZE; 147 #endif 148 149 # endif /* BL32_BASE */ 150 151 /* Populate entry point information for BL33 */ 152 SET_PARAM_HEAD(&bl33_image_ep_info, 153 PARAM_EP, 154 VERSION_1, 155 0); 156 /* 157 * Tell BL31 where the non-trusted software image 158 * is located and the entry state information 159 */ 160 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 161 162 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 163 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 164 165 #if ENABLE_RME 166 /* 167 * Populate entry point information for RMM. 168 * Only PC needs to be set as other fields are determined by RMMD. 169 */ 170 rmm_image_ep_info.pc = RMM_BASE; 171 #endif /* ENABLE_RME */ 172 173 #else /* RESET_TO_BL31 */ 174 175 /* 176 * In debug builds, we pass a special value in 'plat_params_from_bl2' 177 * to verify platform parameters from BL2 to BL31. 178 * In release builds, it's not used. 179 */ 180 assert(((unsigned long long)plat_params_from_bl2) == 181 ARM_BL31_PLAT_PARAM_VAL); 182 183 /* 184 * Check params passed from BL2 should not be NULL, 185 */ 186 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 187 assert(params_from_bl2 != NULL); 188 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 189 assert(params_from_bl2->h.version >= VERSION_2); 190 191 bl_params_node_t *bl_params = params_from_bl2->head; 192 193 /* 194 * Copy BL33, BL32 and RMM (if present), entry point information. 195 * They are stored in Secure RAM, in BL2's address space. 196 */ 197 while (bl_params != NULL) { 198 if (bl_params->image_id == BL32_IMAGE_ID) { 199 bl32_image_ep_info = *bl_params->ep_info; 200 } 201 #if ENABLE_RME 202 else if (bl_params->image_id == RMM_IMAGE_ID) { 203 rmm_image_ep_info = *bl_params->ep_info; 204 } 205 #endif 206 else if (bl_params->image_id == BL33_IMAGE_ID) { 207 bl33_image_ep_info = *bl_params->ep_info; 208 } 209 210 bl_params = bl_params->next_params_info; 211 } 212 213 if (bl33_image_ep_info.pc == 0U) 214 panic(); 215 #if ENABLE_RME 216 if (rmm_image_ep_info.pc == 0U) 217 panic(); 218 #endif 219 #endif /* RESET_TO_BL31 */ 220 221 # if ARM_LINUX_KERNEL_AS_BL33 222 /* 223 * According to the file ``Documentation/arm64/booting.txt`` of the 224 * Linux kernel tree, Linux expects the physical address of the device 225 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and 226 * must be 0. 227 * Repurpose the option to load Hafnium hypervisor in the normal world. 228 * It expects its manifest address in x0. This is essentially the linux 229 * dts (passed to the primary VM) by adding 'hypervisor' and chosen 230 * nodes specifying the Hypervisor configuration. 231 */ 232 #if RESET_TO_BL31 233 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; 234 #else 235 bl33_image_ep_info.args.arg0 = (u_register_t)hw_config; 236 #endif 237 bl33_image_ep_info.args.arg1 = 0U; 238 bl33_image_ep_info.args.arg2 = 0U; 239 bl33_image_ep_info.args.arg3 = 0U; 240 # endif 241 } 242 243 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 244 u_register_t arg2, u_register_t arg3) 245 { 246 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 247 248 /* 249 * Initialize Interconnect for this cluster during cold boot. 250 * No need for locks as no other CPU is active. 251 */ 252 plat_arm_interconnect_init(); 253 254 /* 255 * Enable Interconnect coherency for the primary CPU's cluster. 256 * Earlier bootloader stages might already do this (e.g. Trusted 257 * Firmware's BL1 does it) but we can't assume so. There is no harm in 258 * executing this code twice anyway. 259 * Platform specific PSCI code will enable coherency for other 260 * clusters. 261 */ 262 plat_arm_interconnect_enter_coherency(); 263 } 264 265 /******************************************************************************* 266 * Perform any BL31 platform setup common to ARM standard platforms 267 ******************************************************************************/ 268 void arm_bl31_platform_setup(void) 269 { 270 /* Initialize the GIC driver, cpu and distributor interfaces */ 271 plat_arm_gic_driver_init(); 272 plat_arm_gic_init(); 273 274 #if RESET_TO_BL31 275 /* 276 * Do initial security configuration to allow DRAM/device access 277 * (if earlier BL has not already done so). 278 */ 279 plat_arm_security_setup(); 280 281 #if defined(PLAT_ARM_MEM_PROT_ADDR) 282 arm_nor_psci_do_dyn_mem_protect(); 283 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 284 285 #endif /* RESET_TO_BL31 */ 286 287 /* Enable and initialize the System level generic timer */ 288 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 289 CNTCR_FCREQ(0U) | CNTCR_EN); 290 291 /* Allow access to the System counter timer module */ 292 arm_configure_sys_timer(); 293 294 /* Initialize power controller before setting up topology */ 295 plat_arm_pwrc_setup(); 296 297 #if RAS_EXTENSION 298 ras_init(); 299 #endif 300 301 #if USE_DEBUGFS 302 debugfs_init(); 303 #endif /* USE_DEBUGFS */ 304 } 305 306 /******************************************************************************* 307 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM 308 * standard platforms 309 * Perform BL31 platform setup 310 ******************************************************************************/ 311 void arm_bl31_plat_runtime_setup(void) 312 { 313 console_switch_state(CONSOLE_FLAG_RUNTIME); 314 315 /* Initialize the runtime console */ 316 arm_console_runtime_init(); 317 318 #if RECLAIM_INIT_CODE 319 arm_free_init_memory(); 320 #endif 321 322 #if PLAT_RO_XLAT_TABLES 323 arm_xlat_make_tables_readonly(); 324 #endif 325 } 326 327 #if RECLAIM_INIT_CODE 328 /* 329 * Make memory for image boot time code RW to reclaim it as stack for the 330 * secondary cores, or RO where it cannot be reclaimed: 331 * 332 * |-------- INIT SECTION --------| 333 * ----------------------------------------- 334 * | CORE 0 | CORE 1 | CORE 2 | EXTRA | 335 * | STACK | STACK | STACK | SPACE | 336 * ----------------------------------------- 337 * <-------------------> <------> 338 * MAKE RW AND XN MAKE 339 * FOR STACKS RO AND XN 340 */ 341 void arm_free_init_memory(void) 342 { 343 int ret = 0; 344 345 if (BL_STACKS_END < BL_INIT_CODE_END) { 346 /* Reclaim some of the init section as stack if possible. */ 347 if (BL_INIT_CODE_BASE < BL_STACKS_END) { 348 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE, 349 BL_STACKS_END - BL_INIT_CODE_BASE, 350 MT_RW_DATA); 351 } 352 /* Make the rest of the init section read-only. */ 353 ret |= xlat_change_mem_attributes(BL_STACKS_END, 354 BL_INIT_CODE_END - BL_STACKS_END, 355 MT_RO_DATA); 356 } else { 357 /* The stacks cover the init section, so reclaim it all. */ 358 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE, 359 BL_INIT_CODE_END - BL_INIT_CODE_BASE, 360 MT_RW_DATA); 361 } 362 363 if (ret != 0) { 364 ERROR("Could not reclaim initialization code"); 365 panic(); 366 } 367 } 368 #endif 369 370 void __init bl31_platform_setup(void) 371 { 372 arm_bl31_platform_setup(); 373 } 374 375 void bl31_plat_runtime_setup(void) 376 { 377 arm_bl31_plat_runtime_setup(); 378 } 379 380 /******************************************************************************* 381 * Perform the very early platform specific architectural setup shared between 382 * ARM standard platforms. This only does basic initialization. Later 383 * architectural setup (bl31_arch_setup()) does not do anything platform 384 * specific. 385 ******************************************************************************/ 386 void __init arm_bl31_plat_arch_setup(void) 387 { 388 const mmap_region_t bl_regions[] = { 389 MAP_BL31_TOTAL, 390 #if ENABLE_RME 391 ARM_MAP_L0_GPT_REGION, 392 #endif 393 #if RECLAIM_INIT_CODE 394 MAP_BL_INIT_CODE, 395 #endif 396 #if SEPARATE_NOBITS_REGION 397 MAP_BL31_NOBITS, 398 #endif 399 ARM_MAP_BL_RO, 400 #if USE_ROMLIB 401 ARM_MAP_ROMLIB_CODE, 402 ARM_MAP_ROMLIB_DATA, 403 #endif 404 #if USE_COHERENT_MEM 405 ARM_MAP_BL_COHERENT_RAM, 406 #endif 407 {0} 408 }; 409 410 setup_page_tables(bl_regions, plat_arm_get_mmap()); 411 412 enable_mmu_el3(0); 413 414 #if ENABLE_RME 415 /* 416 * Initialise Granule Protection library and enable GPC for the primary 417 * processor. The tables have already been initialized by a previous BL 418 * stage, so there is no need to provide any PAS here. This function 419 * sets up pointers to those tables. 420 */ 421 if (gpt_runtime_init() < 0) { 422 ERROR("gpt_runtime_init() failed!\n"); 423 panic(); 424 } 425 #endif /* ENABLE_RME */ 426 427 arm_setup_romlib(); 428 } 429 430 void __init bl31_plat_arch_setup(void) 431 { 432 arm_bl31_plat_arch_setup(); 433 } 434