1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <common/desc_image_load.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <lib/fconf/fconf.h> 18 #include <lib/fconf/fconf_dyn_cfg_getter.h> 19 #ifdef SPD_opteed 20 #include <lib/optee_utils.h> 21 #endif 22 #include <lib/utils.h> 23 #include <plat/arm/common/plat_arm.h> 24 #include <plat/common/platform.h> 25 26 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 27 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 28 29 /* 30 * Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is 31 * for `meminfo_t` data structure and fw_configs passed from BL1. 32 */ 33 CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows); 34 35 /* Weak definitions may be overridden in specific ARM standard platform */ 36 #pragma weak bl2_early_platform_setup2 37 #pragma weak bl2_platform_setup 38 #pragma weak bl2_plat_arch_setup 39 #pragma weak bl2_plat_sec_mem_layout 40 41 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 42 bl2_tzram_layout.total_base, \ 43 bl2_tzram_layout.total_size, \ 44 MT_MEMORY | MT_RW | MT_SECURE) 45 46 47 #pragma weak arm_bl2_plat_handle_post_image_load 48 49 /******************************************************************************* 50 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 51 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 52 * Copy it to a safe location before its reclaimed by later BL2 functionality. 53 ******************************************************************************/ 54 void arm_bl2_early_platform_setup(uintptr_t fw_config, 55 struct meminfo *mem_layout) 56 { 57 const struct dyn_cfg_dtb_info_t *tb_fw_config_info; 58 /* Initialize the console to provide early debug support */ 59 arm_console_boot_init(); 60 61 /* Setup the BL2 memory layout */ 62 bl2_tzram_layout = *mem_layout; 63 64 /* Fill the properties struct with the info from the config dtb */ 65 if (fw_config != 0U) { 66 fconf_populate("FW_CONFIG", fw_config); 67 } 68 69 /* TB_FW_CONFIG was also loaded by BL1 */ 70 tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID); 71 if (tb_fw_config_info != NULL) { 72 fconf_populate("TB_FW", tb_fw_config_info->config_addr); 73 } 74 75 /* Initialise the IO layer and register platform IO devices */ 76 plat_arm_io_setup(); 77 } 78 79 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 80 { 81 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 82 83 generic_delay_timer_init(); 84 } 85 86 /* 87 * Perform BL2 preload setup. Currently we initialise the dynamic 88 * configuration here. 89 */ 90 void bl2_plat_preload_setup(void) 91 { 92 arm_bl2_dyn_cfg_init(); 93 } 94 95 /* 96 * Perform ARM standard platform setup. 97 */ 98 void arm_bl2_platform_setup(void) 99 { 100 /* Initialize the secure environment */ 101 plat_arm_security_setup(); 102 103 #if defined(PLAT_ARM_MEM_PROT_ADDR) 104 arm_nor_psci_do_static_mem_protect(); 105 #endif 106 } 107 108 void bl2_platform_setup(void) 109 { 110 arm_bl2_platform_setup(); 111 } 112 113 /******************************************************************************* 114 * Perform the very early platform specific architectural setup here. At the 115 * moment this is only initializes the mmu in a quick and dirty way. 116 ******************************************************************************/ 117 void arm_bl2_plat_arch_setup(void) 118 { 119 #if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG 120 /* 121 * Ensure ARM platforms don't use coherent memory in BL2 unless 122 * cryptocell integration is enabled. 123 */ 124 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 125 #endif 126 127 const mmap_region_t bl_regions[] = { 128 MAP_BL2_TOTAL, 129 ARM_MAP_BL_RO, 130 #if USE_ROMLIB 131 ARM_MAP_ROMLIB_CODE, 132 ARM_MAP_ROMLIB_DATA, 133 #endif 134 #if ARM_CRYPTOCELL_INTEG 135 ARM_MAP_BL_COHERENT_RAM, 136 #endif 137 {0} 138 }; 139 140 setup_page_tables(bl_regions, plat_arm_get_mmap()); 141 142 #ifdef __aarch64__ 143 enable_mmu_el1(0); 144 #else 145 enable_mmu_svc_mon(0); 146 #endif 147 148 arm_setup_romlib(); 149 } 150 151 void bl2_plat_arch_setup(void) 152 { 153 arm_bl2_plat_arch_setup(); 154 } 155 156 int arm_bl2_handle_post_image_load(unsigned int image_id) 157 { 158 int err = 0; 159 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 160 #ifdef SPD_opteed 161 bl_mem_params_node_t *pager_mem_params = NULL; 162 bl_mem_params_node_t *paged_mem_params = NULL; 163 #endif 164 assert(bl_mem_params != NULL); 165 166 switch (image_id) { 167 #ifdef __aarch64__ 168 case BL32_IMAGE_ID: 169 #ifdef SPD_opteed 170 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 171 assert(pager_mem_params); 172 173 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 174 assert(paged_mem_params); 175 176 err = parse_optee_header(&bl_mem_params->ep_info, 177 &pager_mem_params->image_info, 178 &paged_mem_params->image_info); 179 if (err != 0) { 180 WARN("OPTEE header parse error.\n"); 181 } 182 #endif 183 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 184 break; 185 #endif 186 187 case BL33_IMAGE_ID: 188 /* BL33 expects to receive the primary CPU MPID (through r0) */ 189 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 190 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 191 break; 192 193 #ifdef SCP_BL2_BASE 194 case SCP_BL2_IMAGE_ID: 195 /* The subsequent handling of SCP_BL2 is platform specific */ 196 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 197 if (err) { 198 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 199 } 200 break; 201 #endif 202 default: 203 /* Do nothing in default case */ 204 break; 205 } 206 207 return err; 208 } 209 210 /******************************************************************************* 211 * This function can be used by the platforms to update/use image 212 * information for given `image_id`. 213 ******************************************************************************/ 214 int arm_bl2_plat_handle_post_image_load(unsigned int image_id) 215 { 216 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 217 /* For Secure Partitions we don't need post processing */ 218 if ((image_id >= (MAX_NUMBER_IDS - MAX_SP_IDS)) && 219 (image_id < MAX_NUMBER_IDS)) { 220 return 0; 221 } 222 #endif 223 return arm_bl2_handle_post_image_load(image_id); 224 } 225 226 int bl2_plat_handle_post_image_load(unsigned int image_id) 227 { 228 return arm_bl2_plat_handle_post_image_load(image_id); 229 } 230