1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <common/desc_image_load.h> 16 #include <drivers/generic_delay_timer.h> 17 #ifdef SPD_opteed 18 #include <lib/optee_utils.h> 19 #endif 20 #include <lib/utils.h> 21 #include <plat/common/platform.h> 22 23 #include <plat_arm.h> 24 25 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 26 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 27 28 /* 29 * Check that BL2_BASE is above ARM_TB_FW_CONFIG_LIMIT. This reserved page is 30 * for `meminfo_t` data structure and fw_configs passed from BL1. 31 */ 32 CASSERT(BL2_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl2_base_overflows); 33 34 /* Weak definitions may be overridden in specific ARM standard platform */ 35 #pragma weak bl2_early_platform_setup2 36 #pragma weak bl2_platform_setup 37 #pragma weak bl2_plat_arch_setup 38 #pragma weak bl2_plat_sec_mem_layout 39 40 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 41 bl2_tzram_layout.total_base, \ 42 bl2_tzram_layout.total_size, \ 43 MT_MEMORY | MT_RW | MT_SECURE) 44 45 46 #pragma weak arm_bl2_plat_handle_post_image_load 47 48 /******************************************************************************* 49 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 50 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 51 * Copy it to a safe location before its reclaimed by later BL2 functionality. 52 ******************************************************************************/ 53 void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, 54 struct meminfo *mem_layout) 55 { 56 /* Initialize the console to provide early debug support */ 57 arm_console_boot_init(); 58 59 /* Setup the BL2 memory layout */ 60 bl2_tzram_layout = *mem_layout; 61 62 /* Initialise the IO layer and register platform IO devices */ 63 plat_arm_io_setup(); 64 65 if (tb_fw_config != 0U) 66 arm_bl2_set_tb_cfg_addr((void *)tb_fw_config); 67 } 68 69 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 70 { 71 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 72 73 generic_delay_timer_init(); 74 } 75 76 /* 77 * Perform BL2 preload setup. Currently we initialise the dynamic 78 * configuration here. 79 */ 80 void bl2_plat_preload_setup(void) 81 { 82 arm_bl2_dyn_cfg_init(); 83 } 84 85 /* 86 * Perform ARM standard platform setup. 87 */ 88 void arm_bl2_platform_setup(void) 89 { 90 /* Initialize the secure environment */ 91 plat_arm_security_setup(); 92 93 #if defined(PLAT_ARM_MEM_PROT_ADDR) 94 arm_nor_psci_do_static_mem_protect(); 95 #endif 96 } 97 98 void bl2_platform_setup(void) 99 { 100 arm_bl2_platform_setup(); 101 } 102 103 /******************************************************************************* 104 * Perform the very early platform specific architectural setup here. At the 105 * moment this is only initializes the mmu in a quick and dirty way. 106 ******************************************************************************/ 107 void arm_bl2_plat_arch_setup(void) 108 { 109 #if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG 110 /* 111 * Ensure ARM platforms don't use coherent memory in BL2 unless 112 * cryptocell integration is enabled. 113 */ 114 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 115 #endif 116 117 const mmap_region_t bl_regions[] = { 118 MAP_BL2_TOTAL, 119 ARM_MAP_BL_RO, 120 #if USE_ROMLIB 121 ARM_MAP_ROMLIB_CODE, 122 ARM_MAP_ROMLIB_DATA, 123 #endif 124 #if ARM_CRYPTOCELL_INTEG 125 ARM_MAP_BL_COHERENT_RAM, 126 #endif 127 {0} 128 }; 129 130 setup_page_tables(bl_regions, plat_arm_get_mmap()); 131 132 #ifdef AARCH32 133 enable_mmu_svc_mon(0); 134 #else 135 enable_mmu_el1(0); 136 #endif 137 138 arm_setup_romlib(); 139 } 140 141 void bl2_plat_arch_setup(void) 142 { 143 arm_bl2_plat_arch_setup(); 144 } 145 146 int arm_bl2_handle_post_image_load(unsigned int image_id) 147 { 148 int err = 0; 149 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 150 #ifdef SPD_opteed 151 bl_mem_params_node_t *pager_mem_params = NULL; 152 bl_mem_params_node_t *paged_mem_params = NULL; 153 #endif 154 assert(bl_mem_params); 155 156 switch (image_id) { 157 #ifdef AARCH64 158 case BL32_IMAGE_ID: 159 #ifdef SPD_opteed 160 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 161 assert(pager_mem_params); 162 163 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 164 assert(paged_mem_params); 165 166 err = parse_optee_header(&bl_mem_params->ep_info, 167 &pager_mem_params->image_info, 168 &paged_mem_params->image_info); 169 if (err != 0) { 170 WARN("OPTEE header parse error.\n"); 171 } 172 #endif 173 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 174 break; 175 #endif 176 177 case BL33_IMAGE_ID: 178 /* BL33 expects to receive the primary CPU MPID (through r0) */ 179 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 180 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 181 break; 182 183 #ifdef SCP_BL2_BASE 184 case SCP_BL2_IMAGE_ID: 185 /* The subsequent handling of SCP_BL2 is platform specific */ 186 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 187 if (err) { 188 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 189 } 190 break; 191 #endif 192 default: 193 /* Do nothing in default case */ 194 break; 195 } 196 197 return err; 198 } 199 200 /******************************************************************************* 201 * This function can be used by the platforms to update/use image 202 * information for given `image_id`. 203 ******************************************************************************/ 204 int arm_bl2_plat_handle_post_image_load(unsigned int image_id) 205 { 206 return arm_bl2_handle_post_image_load(image_id); 207 } 208 209 int bl2_plat_handle_post_image_load(unsigned int image_id) 210 { 211 return arm_bl2_plat_handle_post_image_load(image_id); 212 } 213