1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <arm_def.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <console.h> 12 #include <debug.h> 13 #include <desc_image_load.h> 14 #include <generic_delay_timer.h> 15 #ifdef SPD_opteed 16 #include <optee_utils.h> 17 #endif 18 #include <plat_arm.h> 19 #include <platform.h> 20 #include <platform_def.h> 21 #include <string.h> 22 #include <utils.h> 23 24 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 25 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 26 27 /* 28 * Check that BL2_BASE is atleast a page over ARM_BL_RAM_BASE. The page is for 29 * `meminfo_t` data structure and TB_FW_CONFIG passed from BL1. Not needed 30 * when BL2 is compiled for BL_AT_EL3 as BL2 doesn't need any info from BL1 and 31 * BL2 is loaded at base of usable SRAM. 32 */ 33 #if BL2_AT_EL3 34 #define BL1_MEMINFO_OFFSET 0x0 35 #else 36 #define BL1_MEMINFO_OFFSET PAGE_SIZE 37 #endif 38 39 CASSERT(BL2_BASE >= (ARM_BL_RAM_BASE + BL1_MEMINFO_OFFSET), assert_bl2_base_overflows); 40 41 /* Weak definitions may be overridden in specific ARM standard platform */ 42 #pragma weak bl2_early_platform_setup2 43 #pragma weak bl2_platform_setup 44 #pragma weak bl2_plat_arch_setup 45 #pragma weak bl2_plat_sec_mem_layout 46 47 #if !LOAD_IMAGE_V2 48 /******************************************************************************* 49 * This structure represents the superset of information that is passed to 50 * BL31, e.g. while passing control to it from BL2, bl31_params 51 * and other platform specific params 52 ******************************************************************************/ 53 typedef struct bl2_to_bl31_params_mem { 54 bl31_params_t bl31_params; 55 image_info_t bl31_image_info; 56 image_info_t bl32_image_info; 57 image_info_t bl33_image_info; 58 entry_point_info_t bl33_ep_info; 59 entry_point_info_t bl32_ep_info; 60 entry_point_info_t bl31_ep_info; 61 } bl2_to_bl31_params_mem_t; 62 63 64 static bl2_to_bl31_params_mem_t bl31_params_mem; 65 66 67 /* Weak definitions may be overridden in specific ARM standard platform */ 68 #pragma weak bl2_plat_get_bl31_params 69 #pragma weak bl2_plat_get_bl31_ep_info 70 #pragma weak bl2_plat_flush_bl31_params 71 #pragma weak bl2_plat_set_bl31_ep_info 72 #pragma weak bl2_plat_get_scp_bl2_meminfo 73 #pragma weak bl2_plat_get_bl32_meminfo 74 #pragma weak bl2_plat_set_bl32_ep_info 75 #pragma weak bl2_plat_get_bl33_meminfo 76 #pragma weak bl2_plat_set_bl33_ep_info 77 78 #if ARM_BL31_IN_DRAM 79 meminfo_t *bl2_plat_sec_mem_layout(void) 80 { 81 static meminfo_t bl2_dram_layout 82 __aligned(CACHE_WRITEBACK_GRANULE) = { 83 .total_base = BL31_BASE, 84 .total_size = (ARM_AP_TZC_DRAM1_BASE + 85 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE, 86 .free_base = BL31_BASE, 87 .free_size = (ARM_AP_TZC_DRAM1_BASE + 88 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE 89 }; 90 91 return &bl2_dram_layout; 92 } 93 #else 94 meminfo_t *bl2_plat_sec_mem_layout(void) 95 { 96 return &bl2_tzram_layout; 97 } 98 #endif /* ARM_BL31_IN_DRAM */ 99 100 /******************************************************************************* 101 * This function assigns a pointer to the memory that the platform has kept 102 * aside to pass platform specific and trusted firmware related information 103 * to BL31. This memory is allocated by allocating memory to 104 * bl2_to_bl31_params_mem_t structure which is a superset of all the 105 * structure whose information is passed to BL31 106 * NOTE: This function should be called only once and should be done 107 * before generating params to BL31 108 ******************************************************************************/ 109 bl31_params_t *bl2_plat_get_bl31_params(void) 110 { 111 bl31_params_t *bl2_to_bl31_params; 112 113 /* 114 * Initialise the memory for all the arguments that needs to 115 * be passed to BL31 116 */ 117 zeromem(&bl31_params_mem, sizeof(bl2_to_bl31_params_mem_t)); 118 119 /* Assign memory for TF related information */ 120 bl2_to_bl31_params = &bl31_params_mem.bl31_params; 121 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); 122 123 /* Fill BL31 related information */ 124 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info; 125 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY, 126 VERSION_1, 0); 127 128 /* Fill BL32 related information if it exists */ 129 #ifdef BL32_BASE 130 bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; 131 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP, 132 VERSION_1, 0); 133 bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; 134 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY, 135 VERSION_1, 0); 136 #endif /* BL32_BASE */ 137 138 /* Fill BL33 related information */ 139 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; 140 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, 141 PARAM_EP, VERSION_1, 0); 142 143 /* BL33 expects to receive the primary CPU MPID (through x0) */ 144 bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); 145 146 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; 147 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY, 148 VERSION_1, 0); 149 150 return bl2_to_bl31_params; 151 } 152 153 /* Flush the TF params and the TF plat params */ 154 void bl2_plat_flush_bl31_params(void) 155 { 156 flush_dcache_range((unsigned long)&bl31_params_mem, 157 sizeof(bl2_to_bl31_params_mem_t)); 158 } 159 160 /******************************************************************************* 161 * This function returns a pointer to the shared memory that the platform 162 * has kept to point to entry point information of BL31 to BL2 163 ******************************************************************************/ 164 struct entry_point_info *bl2_plat_get_bl31_ep_info(void) 165 { 166 #if DEBUG 167 bl31_params_mem.bl31_ep_info.args.arg3 = ARM_BL31_PLAT_PARAM_VAL; 168 #endif 169 170 return &bl31_params_mem.bl31_ep_info; 171 } 172 #endif /* LOAD_IMAGE_V2 */ 173 174 /******************************************************************************* 175 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 176 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 177 * Copy it to a safe location before its reclaimed by later BL2 functionality. 178 ******************************************************************************/ 179 void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, meminfo_t *mem_layout) 180 { 181 /* Initialize the console to provide early debug support */ 182 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 183 ARM_CONSOLE_BAUDRATE); 184 185 /* Setup the BL2 memory layout */ 186 bl2_tzram_layout = *mem_layout; 187 188 /* Initialise the IO layer and register platform IO devices */ 189 plat_arm_io_setup(); 190 191 #if LOAD_IMAGE_V2 192 if (tb_fw_config != 0U) 193 arm_bl2_set_tb_cfg_addr((void *)tb_fw_config); 194 #endif 195 } 196 197 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 198 { 199 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 200 201 generic_delay_timer_init(); 202 } 203 204 /* 205 * Perform BL2 preload setup. Currently we initialise the dynamic 206 * configuration here. 207 */ 208 void bl2_plat_preload_setup(void) 209 { 210 #if LOAD_IMAGE_V2 211 arm_bl2_dyn_cfg_init(); 212 #endif 213 } 214 215 /* 216 * Perform ARM standard platform setup. 217 */ 218 void arm_bl2_platform_setup(void) 219 { 220 /* Initialize the secure environment */ 221 plat_arm_security_setup(); 222 223 #if defined(PLAT_ARM_MEM_PROT_ADDR) 224 arm_nor_psci_do_static_mem_protect(); 225 #endif 226 } 227 228 void bl2_platform_setup(void) 229 { 230 arm_bl2_platform_setup(); 231 } 232 233 /******************************************************************************* 234 * Perform the very early platform specific architectural setup here. At the 235 * moment this is only initializes the mmu in a quick and dirty way. 236 ******************************************************************************/ 237 void arm_bl2_plat_arch_setup(void) 238 { 239 arm_setup_page_tables(bl2_tzram_layout.total_base, 240 bl2_tzram_layout.total_size, 241 BL_CODE_BASE, 242 BL_CODE_END, 243 BL_RO_DATA_BASE, 244 BL_RO_DATA_END 245 #if USE_COHERENT_MEM 246 , BL_COHERENT_RAM_BASE, 247 BL_COHERENT_RAM_END 248 #endif 249 ); 250 251 #ifdef AARCH32 252 enable_mmu_secure(0); 253 #else 254 enable_mmu_el1(0); 255 #endif 256 } 257 258 void bl2_plat_arch_setup(void) 259 { 260 arm_bl2_plat_arch_setup(); 261 } 262 263 #if LOAD_IMAGE_V2 264 int arm_bl2_handle_post_image_load(unsigned int image_id) 265 { 266 int err = 0; 267 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 268 #ifdef SPD_opteed 269 bl_mem_params_node_t *pager_mem_params = NULL; 270 bl_mem_params_node_t *paged_mem_params = NULL; 271 #endif 272 assert(bl_mem_params); 273 274 switch (image_id) { 275 #ifdef AARCH64 276 case BL32_IMAGE_ID: 277 #ifdef SPD_opteed 278 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 279 assert(pager_mem_params); 280 281 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 282 assert(paged_mem_params); 283 284 err = parse_optee_header(&bl_mem_params->ep_info, 285 &pager_mem_params->image_info, 286 &paged_mem_params->image_info); 287 if (err != 0) { 288 WARN("OPTEE header parse error.\n"); 289 } 290 #endif 291 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 292 break; 293 #endif 294 295 case BL33_IMAGE_ID: 296 /* BL33 expects to receive the primary CPU MPID (through r0) */ 297 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 298 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 299 break; 300 301 #ifdef SCP_BL2_BASE 302 case SCP_BL2_IMAGE_ID: 303 /* The subsequent handling of SCP_BL2 is platform specific */ 304 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 305 if (err) { 306 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 307 } 308 break; 309 #endif 310 default: 311 /* Do nothing in default case */ 312 break; 313 } 314 315 return err; 316 } 317 318 /******************************************************************************* 319 * This function can be used by the platforms to update/use image 320 * information for given `image_id`. 321 ******************************************************************************/ 322 int bl2_plat_handle_post_image_load(unsigned int image_id) 323 { 324 return arm_bl2_handle_post_image_load(image_id); 325 } 326 327 #else /* LOAD_IMAGE_V2 */ 328 329 /******************************************************************************* 330 * Populate the extents of memory available for loading SCP_BL2 (if used), 331 * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2. 332 ******************************************************************************/ 333 void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo) 334 { 335 *scp_bl2_meminfo = bl2_tzram_layout; 336 } 337 338 /******************************************************************************* 339 * Before calling this function BL31 is loaded in memory and its entrypoint 340 * is set by load_image. This is a placeholder for the platform to change 341 * the entrypoint of BL31 and set SPSR and security state. 342 * On ARM standard platforms we only set the security state of the entrypoint 343 ******************************************************************************/ 344 void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info, 345 entry_point_info_t *bl31_ep_info) 346 { 347 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); 348 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, 349 DISABLE_ALL_EXCEPTIONS); 350 } 351 352 353 /******************************************************************************* 354 * Before calling this function BL32 is loaded in memory and its entrypoint 355 * is set by load_image. This is a placeholder for the platform to change 356 * the entrypoint of BL32 and set SPSR and security state. 357 * On ARM standard platforms we only set the security state of the entrypoint 358 ******************************************************************************/ 359 #ifdef BL32_BASE 360 void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, 361 entry_point_info_t *bl32_ep_info) 362 { 363 SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); 364 bl32_ep_info->spsr = arm_get_spsr_for_bl32_entry(); 365 } 366 367 /******************************************************************************* 368 * Populate the extents of memory available for loading BL32 369 ******************************************************************************/ 370 void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) 371 { 372 /* 373 * Populate the extents of memory available for loading BL32. 374 */ 375 bl32_meminfo->total_base = BL32_BASE; 376 bl32_meminfo->free_base = BL32_BASE; 377 bl32_meminfo->total_size = 378 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 379 bl32_meminfo->free_size = 380 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 381 } 382 #endif /* BL32_BASE */ 383 384 /******************************************************************************* 385 * Before calling this function BL33 is loaded in memory and its entrypoint 386 * is set by load_image. This is a placeholder for the platform to change 387 * the entrypoint of BL33 and set SPSR and security state. 388 * On ARM standard platforms we only set the security state of the entrypoint 389 ******************************************************************************/ 390 void bl2_plat_set_bl33_ep_info(image_info_t *image, 391 entry_point_info_t *bl33_ep_info) 392 { 393 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); 394 bl33_ep_info->spsr = arm_get_spsr_for_bl33_entry(); 395 } 396 397 /******************************************************************************* 398 * Populate the extents of memory available for loading BL33 399 ******************************************************************************/ 400 void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) 401 { 402 bl33_meminfo->total_base = ARM_NS_DRAM1_BASE; 403 bl33_meminfo->total_size = ARM_NS_DRAM1_SIZE; 404 bl33_meminfo->free_base = ARM_NS_DRAM1_BASE; 405 bl33_meminfo->free_size = ARM_NS_DRAM1_SIZE; 406 } 407 408 #endif /* LOAD_IMAGE_V2 */ 409