1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_features.h> 13 #include <arch_helpers.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <common/desc_image_load.h> 17 #include <drivers/generic_delay_timer.h> 18 #include <drivers/partition/partition.h> 19 #include <lib/fconf/fconf.h> 20 #include <lib/fconf/fconf_dyn_cfg_getter.h> 21 #include <lib/gpt_rme/gpt_rme.h> 22 #if TRANSFER_LIST 23 #include <lib/transfer_list.h> 24 #endif 25 #ifdef SPD_opteed 26 #include <lib/optee_utils.h> 27 #endif 28 #include <lib/utils.h> 29 #include <plat/arm/common/plat_arm.h> 30 #include <plat/common/platform.h> 31 32 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 33 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 34 35 /* Base address of fw_config received from BL1 */ 36 static uintptr_t config_base __unused; 37 38 /* 39 * Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is 40 * for `meminfo_t` data structure and fw_configs passed from BL1. 41 */ 42 #if TRANSFER_LIST 43 CASSERT(BL2_BASE >= PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE, 44 assert_bl2_base_overflows); 45 #else 46 CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows); 47 #endif /* TRANSFER_LIST */ 48 49 /* Weak definitions may be overridden in specific ARM standard platform */ 50 #pragma weak bl2_early_platform_setup2 51 #pragma weak bl2_platform_setup 52 #pragma weak bl2_plat_arch_setup 53 #pragma weak bl2_plat_sec_mem_layout 54 55 #if ENABLE_RME 56 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 57 bl2_tzram_layout.total_base, \ 58 bl2_tzram_layout.total_size, \ 59 MT_MEMORY | MT_RW | MT_ROOT) 60 #else 61 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 62 bl2_tzram_layout.total_base, \ 63 bl2_tzram_layout.total_size, \ 64 MT_MEMORY | MT_RW | MT_SECURE) 65 #endif /* ENABLE_RME */ 66 67 #pragma weak arm_bl2_plat_handle_post_image_load 68 69 static struct transfer_list_header *secure_tl __unused; 70 static struct transfer_list_header *ns_tl __unused; 71 72 /******************************************************************************* 73 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 74 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 75 * Copy it to a safe location before its reclaimed by later BL2 functionality. 76 ******************************************************************************/ 77 void arm_bl2_early_platform_setup(uintptr_t fw_config, 78 struct meminfo *mem_layout) 79 { 80 struct transfer_list_entry *te __unused; 81 int __maybe_unused ret; 82 83 /* Initialize the console to provide early debug support */ 84 arm_console_boot_init(); 85 86 #if TRANSFER_LIST 87 // TODO: modify the prototype of this function fw_config != bl2_tl 88 secure_tl = (struct transfer_list_header *)fw_config; 89 90 te = transfer_list_find(secure_tl, TL_TAG_SRAM_LAYOUT64); 91 assert(te != NULL); 92 93 bl2_tzram_layout = *(meminfo_t *)transfer_list_entry_data(te); 94 transfer_list_rem(secure_tl, te); 95 #else 96 config_base = fw_config; 97 98 /* Setup the BL2 memory layout */ 99 bl2_tzram_layout = *mem_layout; 100 #endif 101 102 /* Initialise the IO layer and register platform IO devices */ 103 plat_arm_io_setup(); 104 105 /* Load partition table */ 106 #if ARM_GPT_SUPPORT 107 ret = gpt_partition_init(); 108 if (ret != 0) { 109 ERROR("GPT partition initialisation failed!\n"); 110 panic(); 111 } 112 113 #endif /* ARM_GPT_SUPPORT */ 114 } 115 116 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 117 { 118 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 119 120 generic_delay_timer_init(); 121 } 122 123 /* 124 * Perform BL2 preload setup. Currently we initialise the dynamic 125 * configuration here. 126 */ 127 void bl2_plat_preload_setup(void) 128 { 129 #if TRANSFER_LIST 130 /* Assume the secure TL hasn't been initialised if BL2 is running at EL3. */ 131 #if RESET_TO_BL2 132 secure_tl = transfer_list_init((void *)PLAT_ARM_EL3_FW_HANDOFF_BASE, 133 PLAT_ARM_FW_HANDOFF_SIZE); 134 135 if (secure_tl == NULL) { 136 ERROR("Secure transfer list initialisation failed!\n"); 137 panic(); 138 } 139 #endif 140 141 arm_transfer_list_dyn_cfg_init(secure_tl); 142 #else 143 arm_bl2_dyn_cfg_init(); 144 #endif 145 146 #if ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT 147 /* Always use the FIP from bank 0 */ 148 arm_set_fip_addr(0U); 149 #endif /* ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT */ 150 } 151 152 /* 153 * Perform ARM standard platform setup. 154 */ 155 void arm_bl2_platform_setup(void) 156 { 157 #if !ENABLE_RME 158 /* Initialize the secure environment */ 159 plat_arm_security_setup(); 160 #endif 161 162 #if defined(PLAT_ARM_MEM_PROT_ADDR) 163 arm_nor_psci_do_static_mem_protect(); 164 #endif 165 166 #if TRANSFER_LIST 167 ns_tl = transfer_list_init((void *)FW_NS_HANDOFF_BASE, 168 PLAT_ARM_FW_HANDOFF_SIZE); 169 170 if (ns_tl == NULL) { 171 ERROR("Non-secure transfer list initialisation failed!"); 172 panic(); 173 } 174 #endif 175 } 176 177 void bl2_platform_setup(void) 178 { 179 arm_bl2_platform_setup(); 180 } 181 182 /******************************************************************************* 183 * Perform the very early platform specific architectural setup here. 184 * When RME is enabled the secure environment is initialised before 185 * initialising and enabling Granule Protection. 186 * This function initialises the MMU in a quick and dirty way. 187 ******************************************************************************/ 188 void arm_bl2_plat_arch_setup(void) 189 { 190 #if USE_COHERENT_MEM 191 /* Ensure ARM platforms don't use coherent memory in BL2. */ 192 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 193 #endif 194 195 const mmap_region_t bl_regions[] = { 196 MAP_BL2_TOTAL, 197 ARM_MAP_BL_RO, 198 #if USE_ROMLIB 199 ARM_MAP_ROMLIB_CODE, 200 ARM_MAP_ROMLIB_DATA, 201 #endif 202 #if !TRANSFER_LIST 203 ARM_MAP_BL_CONFIG_REGION, 204 #endif /* TRANSFER_LIST */ 205 #if ENABLE_RME 206 ARM_MAP_L0_GPT_REGION, 207 #endif 208 { 0 } 209 }; 210 211 #if ENABLE_RME 212 /* Initialise the secure environment */ 213 plat_arm_security_setup(); 214 #endif 215 setup_page_tables(bl_regions, plat_arm_get_mmap()); 216 217 #ifdef __aarch64__ 218 #if ENABLE_RME 219 /* BL2 runs in EL3 when RME enabled. */ 220 assert(is_feat_rme_present()); 221 enable_mmu_el3(0); 222 223 /* Initialise and enable granule protection after MMU. */ 224 arm_gpt_setup(); 225 #else 226 enable_mmu_el1(0); 227 #endif 228 #else 229 enable_mmu_svc_mon(0); 230 #endif 231 232 arm_setup_romlib(); 233 } 234 235 void bl2_plat_arch_setup(void) 236 { 237 const struct dyn_cfg_dtb_info_t *tb_fw_config_info __unused; 238 struct transfer_list_entry *te __unused; 239 arm_bl2_plat_arch_setup(); 240 241 #if TRANSFER_LIST 242 te = transfer_list_find(secure_tl, TL_TAG_TB_FW_CONFIG); 243 assert(te != NULL); 244 245 fconf_populate("TB_FW", (uintptr_t)transfer_list_entry_data(te)); 246 transfer_list_rem(secure_tl, te); 247 #else 248 /* Fill the properties struct with the info from the config dtb */ 249 fconf_populate("FW_CONFIG", config_base); 250 251 /* TB_FW_CONFIG was also loaded by BL1 */ 252 tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID); 253 assert(tb_fw_config_info != NULL); 254 255 fconf_populate("TB_FW", tb_fw_config_info->config_addr); 256 #endif 257 } 258 259 int arm_bl2_handle_post_image_load(unsigned int image_id) 260 { 261 int err = 0; 262 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 263 #ifdef SPD_opteed 264 bl_mem_params_node_t *pager_mem_params = NULL; 265 bl_mem_params_node_t *paged_mem_params = NULL; 266 #endif 267 assert(bl_mem_params != NULL); 268 269 switch (image_id) { 270 #ifdef __aarch64__ 271 case BL32_IMAGE_ID: 272 #ifdef SPD_opteed 273 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 274 assert(pager_mem_params); 275 276 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 277 assert(paged_mem_params); 278 279 err = parse_optee_header(&bl_mem_params->ep_info, 280 &pager_mem_params->image_info, 281 &paged_mem_params->image_info); 282 if (err != 0) { 283 WARN("OPTEE header parse error.\n"); 284 } 285 #endif 286 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 287 break; 288 #endif 289 290 case BL33_IMAGE_ID: 291 /* BL33 expects to receive the primary CPU MPID (through r0) */ 292 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 293 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 294 break; 295 296 #ifdef SCP_BL2_BASE 297 case SCP_BL2_IMAGE_ID: 298 /* The subsequent handling of SCP_BL2 is platform specific */ 299 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 300 if (err) { 301 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 302 } 303 break; 304 #endif 305 default: 306 /* Do nothing in default case */ 307 break; 308 } 309 310 return err; 311 } 312 313 /******************************************************************************* 314 * This function can be used by the platforms to update/use image 315 * information for given `image_id`. 316 ******************************************************************************/ 317 int arm_bl2_plat_handle_post_image_load(unsigned int image_id) 318 { 319 #if defined(SPD_spmd) && BL2_ENABLE_SP_LOAD 320 /* For Secure Partitions we don't need post processing */ 321 if ((image_id >= (MAX_NUMBER_IDS - MAX_SP_IDS)) && 322 (image_id < MAX_NUMBER_IDS)) { 323 return 0; 324 } 325 #endif 326 327 #if TRANSFER_LIST 328 if (image_id == HW_CONFIG_ID) { 329 arm_transfer_list_copy_hw_config(secure_tl, ns_tl); 330 } 331 #endif /* TRANSFER_LIST */ 332 333 return arm_bl2_handle_post_image_load(image_id); 334 } 335 336 void arm_bl2_setup_next_ep_info(bl_mem_params_node_t *next_param_node) 337 { 338 assert(transfer_list_set_handoff_args( 339 secure_tl, &next_param_node->ep_info) != NULL); 340 341 arm_transfer_list_populate_ep_info(next_param_node, secure_tl, ns_tl); 342 } 343