1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <arm_def.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <console.h> 12 #include <debug.h> 13 #include <desc_image_load.h> 14 #include <generic_delay_timer.h> 15 #ifdef SPD_opteed 16 #include <optee_utils.h> 17 #endif 18 #include <plat_arm.h> 19 #include <platform.h> 20 #include <platform_def.h> 21 #include <string.h> 22 #include <utils.h> 23 24 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 25 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 26 27 /* 28 * Check that BL2_BASE is above ARM_TB_FW_CONFIG_LIMIT. This reserved page is 29 * for `meminfo_t` data structure and fw_configs passed from BL1. 30 */ 31 CASSERT(BL2_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl2_base_overflows); 32 33 /* Weak definitions may be overridden in specific ARM standard platform */ 34 #pragma weak bl2_early_platform_setup2 35 #pragma weak bl2_platform_setup 36 #pragma weak bl2_plat_arch_setup 37 #pragma weak bl2_plat_sec_mem_layout 38 39 #if !LOAD_IMAGE_V2 40 /******************************************************************************* 41 * This structure represents the superset of information that is passed to 42 * BL31, e.g. while passing control to it from BL2, bl31_params 43 * and other platform specific params 44 ******************************************************************************/ 45 typedef struct bl2_to_bl31_params_mem { 46 bl31_params_t bl31_params; 47 image_info_t bl31_image_info; 48 image_info_t bl32_image_info; 49 image_info_t bl33_image_info; 50 entry_point_info_t bl33_ep_info; 51 entry_point_info_t bl32_ep_info; 52 entry_point_info_t bl31_ep_info; 53 } bl2_to_bl31_params_mem_t; 54 55 56 static bl2_to_bl31_params_mem_t bl31_params_mem; 57 58 59 /* Weak definitions may be overridden in specific ARM standard platform */ 60 #pragma weak bl2_plat_get_bl31_params 61 #pragma weak bl2_plat_get_bl31_ep_info 62 #pragma weak bl2_plat_flush_bl31_params 63 #pragma weak bl2_plat_set_bl31_ep_info 64 #pragma weak bl2_plat_get_scp_bl2_meminfo 65 #pragma weak bl2_plat_get_bl32_meminfo 66 #pragma weak bl2_plat_set_bl32_ep_info 67 #pragma weak bl2_plat_get_bl33_meminfo 68 #pragma weak bl2_plat_set_bl33_ep_info 69 70 #if ARM_BL31_IN_DRAM 71 meminfo_t *bl2_plat_sec_mem_layout(void) 72 { 73 static meminfo_t bl2_dram_layout 74 __aligned(CACHE_WRITEBACK_GRANULE) = { 75 .total_base = BL31_BASE, 76 .total_size = (ARM_AP_TZC_DRAM1_BASE + 77 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE, 78 .free_base = BL31_BASE, 79 .free_size = (ARM_AP_TZC_DRAM1_BASE + 80 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE 81 }; 82 83 return &bl2_dram_layout; 84 } 85 #else 86 meminfo_t *bl2_plat_sec_mem_layout(void) 87 { 88 return &bl2_tzram_layout; 89 } 90 #endif /* ARM_BL31_IN_DRAM */ 91 92 /******************************************************************************* 93 * This function assigns a pointer to the memory that the platform has kept 94 * aside to pass platform specific and trusted firmware related information 95 * to BL31. This memory is allocated by allocating memory to 96 * bl2_to_bl31_params_mem_t structure which is a superset of all the 97 * structure whose information is passed to BL31 98 * NOTE: This function should be called only once and should be done 99 * before generating params to BL31 100 ******************************************************************************/ 101 bl31_params_t *bl2_plat_get_bl31_params(void) 102 { 103 bl31_params_t *bl2_to_bl31_params; 104 105 /* 106 * Initialise the memory for all the arguments that needs to 107 * be passed to BL31 108 */ 109 zeromem(&bl31_params_mem, sizeof(bl2_to_bl31_params_mem_t)); 110 111 /* Assign memory for TF related information */ 112 bl2_to_bl31_params = &bl31_params_mem.bl31_params; 113 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); 114 115 /* Fill BL31 related information */ 116 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info; 117 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY, 118 VERSION_1, 0); 119 120 /* Fill BL32 related information if it exists */ 121 #ifdef BL32_BASE 122 bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; 123 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP, 124 VERSION_1, 0); 125 bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; 126 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY, 127 VERSION_1, 0); 128 #endif /* BL32_BASE */ 129 130 /* Fill BL33 related information */ 131 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; 132 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, 133 PARAM_EP, VERSION_1, 0); 134 135 /* BL33 expects to receive the primary CPU MPID (through x0) */ 136 bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); 137 138 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; 139 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY, 140 VERSION_1, 0); 141 142 return bl2_to_bl31_params; 143 } 144 145 /* Flush the TF params and the TF plat params */ 146 void bl2_plat_flush_bl31_params(void) 147 { 148 flush_dcache_range((unsigned long)&bl31_params_mem, 149 sizeof(bl2_to_bl31_params_mem_t)); 150 } 151 152 /******************************************************************************* 153 * This function returns a pointer to the shared memory that the platform 154 * has kept to point to entry point information of BL31 to BL2 155 ******************************************************************************/ 156 struct entry_point_info *bl2_plat_get_bl31_ep_info(void) 157 { 158 #if DEBUG 159 bl31_params_mem.bl31_ep_info.args.arg3 = ARM_BL31_PLAT_PARAM_VAL; 160 #endif 161 162 return &bl31_params_mem.bl31_ep_info; 163 } 164 #endif /* LOAD_IMAGE_V2 */ 165 166 /******************************************************************************* 167 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 168 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 169 * Copy it to a safe location before its reclaimed by later BL2 functionality. 170 ******************************************************************************/ 171 void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, meminfo_t *mem_layout) 172 { 173 /* Initialize the console to provide early debug support */ 174 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 175 ARM_CONSOLE_BAUDRATE); 176 177 /* Setup the BL2 memory layout */ 178 bl2_tzram_layout = *mem_layout; 179 180 /* Initialise the IO layer and register platform IO devices */ 181 plat_arm_io_setup(); 182 183 #if LOAD_IMAGE_V2 184 if (tb_fw_config != 0U) 185 arm_bl2_set_tb_cfg_addr((void *)tb_fw_config); 186 #endif 187 } 188 189 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 190 { 191 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 192 193 generic_delay_timer_init(); 194 } 195 196 /* 197 * Perform BL2 preload setup. Currently we initialise the dynamic 198 * configuration here. 199 */ 200 void bl2_plat_preload_setup(void) 201 { 202 #if LOAD_IMAGE_V2 203 arm_bl2_dyn_cfg_init(); 204 #endif 205 } 206 207 /* 208 * Perform ARM standard platform setup. 209 */ 210 void arm_bl2_platform_setup(void) 211 { 212 /* Initialize the secure environment */ 213 plat_arm_security_setup(); 214 215 #if defined(PLAT_ARM_MEM_PROT_ADDR) 216 arm_nor_psci_do_static_mem_protect(); 217 #endif 218 } 219 220 void bl2_platform_setup(void) 221 { 222 arm_bl2_platform_setup(); 223 } 224 225 /******************************************************************************* 226 * Perform the very early platform specific architectural setup here. At the 227 * moment this is only initializes the mmu in a quick and dirty way. 228 ******************************************************************************/ 229 void arm_bl2_plat_arch_setup(void) 230 { 231 arm_setup_page_tables(bl2_tzram_layout.total_base, 232 bl2_tzram_layout.total_size, 233 BL_CODE_BASE, 234 BL_CODE_END, 235 BL_RO_DATA_BASE, 236 BL_RO_DATA_END 237 #if USE_COHERENT_MEM 238 , BL_COHERENT_RAM_BASE, 239 BL_COHERENT_RAM_END 240 #endif 241 ); 242 243 #ifdef AARCH32 244 enable_mmu_secure(0); 245 #else 246 enable_mmu_el1(0); 247 #endif 248 } 249 250 void bl2_plat_arch_setup(void) 251 { 252 arm_bl2_plat_arch_setup(); 253 } 254 255 #if LOAD_IMAGE_V2 256 int arm_bl2_handle_post_image_load(unsigned int image_id) 257 { 258 int err = 0; 259 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 260 #ifdef SPD_opteed 261 bl_mem_params_node_t *pager_mem_params = NULL; 262 bl_mem_params_node_t *paged_mem_params = NULL; 263 #endif 264 assert(bl_mem_params); 265 266 switch (image_id) { 267 #ifdef AARCH64 268 case BL32_IMAGE_ID: 269 #ifdef SPD_opteed 270 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 271 assert(pager_mem_params); 272 273 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 274 assert(paged_mem_params); 275 276 err = parse_optee_header(&bl_mem_params->ep_info, 277 &pager_mem_params->image_info, 278 &paged_mem_params->image_info); 279 if (err != 0) { 280 WARN("OPTEE header parse error.\n"); 281 } 282 #endif 283 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 284 break; 285 #endif 286 287 case BL33_IMAGE_ID: 288 /* BL33 expects to receive the primary CPU MPID (through r0) */ 289 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 290 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 291 break; 292 293 #ifdef SCP_BL2_BASE 294 case SCP_BL2_IMAGE_ID: 295 /* The subsequent handling of SCP_BL2 is platform specific */ 296 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 297 if (err) { 298 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 299 } 300 break; 301 #endif 302 default: 303 /* Do nothing in default case */ 304 break; 305 } 306 307 return err; 308 } 309 310 /******************************************************************************* 311 * This function can be used by the platforms to update/use image 312 * information for given `image_id`. 313 ******************************************************************************/ 314 int bl2_plat_handle_post_image_load(unsigned int image_id) 315 { 316 return arm_bl2_handle_post_image_load(image_id); 317 } 318 319 #else /* LOAD_IMAGE_V2 */ 320 321 /******************************************************************************* 322 * Populate the extents of memory available for loading SCP_BL2 (if used), 323 * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2. 324 ******************************************************************************/ 325 void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo) 326 { 327 *scp_bl2_meminfo = bl2_tzram_layout; 328 } 329 330 /******************************************************************************* 331 * Before calling this function BL31 is loaded in memory and its entrypoint 332 * is set by load_image. This is a placeholder for the platform to change 333 * the entrypoint of BL31 and set SPSR and security state. 334 * On ARM standard platforms we only set the security state of the entrypoint 335 ******************************************************************************/ 336 void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info, 337 entry_point_info_t *bl31_ep_info) 338 { 339 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); 340 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, 341 DISABLE_ALL_EXCEPTIONS); 342 } 343 344 345 /******************************************************************************* 346 * Before calling this function BL32 is loaded in memory and its entrypoint 347 * is set by load_image. This is a placeholder for the platform to change 348 * the entrypoint of BL32 and set SPSR and security state. 349 * On ARM standard platforms we only set the security state of the entrypoint 350 ******************************************************************************/ 351 #ifdef BL32_BASE 352 void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, 353 entry_point_info_t *bl32_ep_info) 354 { 355 SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); 356 bl32_ep_info->spsr = arm_get_spsr_for_bl32_entry(); 357 } 358 359 /******************************************************************************* 360 * Populate the extents of memory available for loading BL32 361 ******************************************************************************/ 362 void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) 363 { 364 /* 365 * Populate the extents of memory available for loading BL32. 366 */ 367 bl32_meminfo->total_base = BL32_BASE; 368 bl32_meminfo->free_base = BL32_BASE; 369 bl32_meminfo->total_size = 370 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 371 bl32_meminfo->free_size = 372 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 373 } 374 #endif /* BL32_BASE */ 375 376 /******************************************************************************* 377 * Before calling this function BL33 is loaded in memory and its entrypoint 378 * is set by load_image. This is a placeholder for the platform to change 379 * the entrypoint of BL33 and set SPSR and security state. 380 * On ARM standard platforms we only set the security state of the entrypoint 381 ******************************************************************************/ 382 void bl2_plat_set_bl33_ep_info(image_info_t *image, 383 entry_point_info_t *bl33_ep_info) 384 { 385 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); 386 bl33_ep_info->spsr = arm_get_spsr_for_bl33_entry(); 387 } 388 389 /******************************************************************************* 390 * Populate the extents of memory available for loading BL33 391 ******************************************************************************/ 392 void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) 393 { 394 bl33_meminfo->total_base = ARM_NS_DRAM1_BASE; 395 bl33_meminfo->total_size = ARM_NS_DRAM1_SIZE; 396 bl33_meminfo->free_base = ARM_NS_DRAM1_BASE; 397 bl33_meminfo->free_size = ARM_NS_DRAM1_SIZE; 398 } 399 400 #endif /* LOAD_IMAGE_V2 */ 401