1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_features.h> 13 #include <arch_helpers.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <common/desc_image_load.h> 17 #include <drivers/generic_delay_timer.h> 18 #include <drivers/partition/partition.h> 19 #include <lib/fconf/fconf.h> 20 #include <lib/fconf/fconf_dyn_cfg_getter.h> 21 #include <lib/gpt_rme/gpt_rme.h> 22 #ifdef SPD_opteed 23 #include <lib/optee_utils.h> 24 #endif 25 #include <lib/utils.h> 26 #include <plat/arm/common/plat_arm.h> 27 #include <plat/common/platform.h> 28 29 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 30 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 31 32 /* Base address of fw_config received from BL1 */ 33 static uintptr_t config_base; 34 35 /* 36 * Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is 37 * for `meminfo_t` data structure and fw_configs passed from BL1. 38 */ 39 CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows); 40 41 /* Weak definitions may be overridden in specific ARM standard platform */ 42 #pragma weak bl2_early_platform_setup2 43 #pragma weak bl2_platform_setup 44 #pragma weak bl2_plat_arch_setup 45 #pragma weak bl2_plat_sec_mem_layout 46 47 #if ENABLE_RME 48 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 49 bl2_tzram_layout.total_base, \ 50 bl2_tzram_layout.total_size, \ 51 MT_MEMORY | MT_RW | MT_ROOT) 52 #else 53 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 54 bl2_tzram_layout.total_base, \ 55 bl2_tzram_layout.total_size, \ 56 MT_MEMORY | MT_RW | MT_SECURE) 57 #endif /* ENABLE_RME */ 58 59 #pragma weak arm_bl2_plat_handle_post_image_load 60 61 /******************************************************************************* 62 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 63 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 64 * Copy it to a safe location before its reclaimed by later BL2 functionality. 65 ******************************************************************************/ 66 void arm_bl2_early_platform_setup(uintptr_t fw_config, 67 struct meminfo *mem_layout) 68 { 69 int __maybe_unused ret; 70 71 /* Initialize the console to provide early debug support */ 72 arm_console_boot_init(); 73 74 /* Setup the BL2 memory layout */ 75 bl2_tzram_layout = *mem_layout; 76 77 config_base = fw_config; 78 79 /* Initialise the IO layer and register platform IO devices */ 80 plat_arm_io_setup(); 81 82 /* Load partition table */ 83 #if ARM_GPT_SUPPORT 84 ret = gpt_partition_init(); 85 if (ret != 0) { 86 ERROR("GPT partition initialisation failed!\n"); 87 panic(); 88 } 89 90 #endif /* ARM_GPT_SUPPORT */ 91 } 92 93 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 94 { 95 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 96 97 generic_delay_timer_init(); 98 } 99 100 /* 101 * Perform BL2 preload setup. Currently we initialise the dynamic 102 * configuration here. 103 */ 104 void bl2_plat_preload_setup(void) 105 { 106 arm_bl2_dyn_cfg_init(); 107 108 #if ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT 109 /* Always use the FIP from bank 0 */ 110 arm_set_fip_addr(0U); 111 #endif /* ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT */ 112 } 113 114 /* 115 * Perform ARM standard platform setup. 116 */ 117 void arm_bl2_platform_setup(void) 118 { 119 #if !ENABLE_RME 120 /* Initialize the secure environment */ 121 plat_arm_security_setup(); 122 #endif 123 124 #if defined(PLAT_ARM_MEM_PROT_ADDR) 125 arm_nor_psci_do_static_mem_protect(); 126 #endif 127 } 128 129 void bl2_platform_setup(void) 130 { 131 arm_bl2_platform_setup(); 132 } 133 134 /******************************************************************************* 135 * Perform the very early platform specific architectural setup here. 136 * When RME is enabled the secure environment is initialised before 137 * initialising and enabling Granule Protection. 138 * This function initialises the MMU in a quick and dirty way. 139 ******************************************************************************/ 140 void arm_bl2_plat_arch_setup(void) 141 { 142 #if USE_COHERENT_MEM 143 /* Ensure ARM platforms don't use coherent memory in BL2. */ 144 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 145 #endif 146 147 const mmap_region_t bl_regions[] = { 148 MAP_BL2_TOTAL, 149 ARM_MAP_BL_RO, 150 #if USE_ROMLIB 151 ARM_MAP_ROMLIB_CODE, 152 ARM_MAP_ROMLIB_DATA, 153 #endif 154 ARM_MAP_BL_CONFIG_REGION, 155 #if ENABLE_RME 156 ARM_MAP_L0_GPT_REGION, 157 #endif 158 {0} 159 }; 160 161 #if ENABLE_RME 162 /* Initialise the secure environment */ 163 plat_arm_security_setup(); 164 #endif 165 setup_page_tables(bl_regions, plat_arm_get_mmap()); 166 167 #ifdef __aarch64__ 168 #if ENABLE_RME 169 /* BL2 runs in EL3 when RME enabled. */ 170 assert(get_armv9_2_feat_rme_support() != 0U); 171 enable_mmu_el3(0); 172 173 /* Initialise and enable granule protection after MMU. */ 174 arm_gpt_setup(); 175 #else 176 enable_mmu_el1(0); 177 #endif 178 #else 179 enable_mmu_svc_mon(0); 180 #endif 181 182 arm_setup_romlib(); 183 } 184 185 void bl2_plat_arch_setup(void) 186 { 187 const struct dyn_cfg_dtb_info_t *tb_fw_config_info; 188 189 arm_bl2_plat_arch_setup(); 190 191 /* Fill the properties struct with the info from the config dtb */ 192 fconf_populate("FW_CONFIG", config_base); 193 194 /* TB_FW_CONFIG was also loaded by BL1 */ 195 tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID); 196 assert(tb_fw_config_info != NULL); 197 198 fconf_populate("TB_FW", tb_fw_config_info->config_addr); 199 } 200 201 int arm_bl2_handle_post_image_load(unsigned int image_id) 202 { 203 int err = 0; 204 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 205 #ifdef SPD_opteed 206 bl_mem_params_node_t *pager_mem_params = NULL; 207 bl_mem_params_node_t *paged_mem_params = NULL; 208 #endif 209 assert(bl_mem_params != NULL); 210 211 switch (image_id) { 212 #ifdef __aarch64__ 213 case BL32_IMAGE_ID: 214 #ifdef SPD_opteed 215 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 216 assert(pager_mem_params); 217 218 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 219 assert(paged_mem_params); 220 221 err = parse_optee_header(&bl_mem_params->ep_info, 222 &pager_mem_params->image_info, 223 &paged_mem_params->image_info); 224 if (err != 0) { 225 WARN("OPTEE header parse error.\n"); 226 } 227 #endif 228 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 229 break; 230 #endif 231 232 case BL33_IMAGE_ID: 233 /* BL33 expects to receive the primary CPU MPID (through r0) */ 234 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 235 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 236 break; 237 238 #ifdef SCP_BL2_BASE 239 case SCP_BL2_IMAGE_ID: 240 /* The subsequent handling of SCP_BL2 is platform specific */ 241 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 242 if (err) { 243 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 244 } 245 break; 246 #endif 247 default: 248 /* Do nothing in default case */ 249 break; 250 } 251 252 return err; 253 } 254 255 /******************************************************************************* 256 * This function can be used by the platforms to update/use image 257 * information for given `image_id`. 258 ******************************************************************************/ 259 int arm_bl2_plat_handle_post_image_load(unsigned int image_id) 260 { 261 #if defined(SPD_spmd) && BL2_ENABLE_SP_LOAD 262 /* For Secure Partitions we don't need post processing */ 263 if ((image_id >= (MAX_NUMBER_IDS - MAX_SP_IDS)) && 264 (image_id < MAX_NUMBER_IDS)) { 265 return 0; 266 } 267 #endif 268 return arm_bl2_handle_post_image_load(image_id); 269 } 270