1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <arm_def.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <console.h> 12 #include <debug.h> 13 #include <desc_image_load.h> 14 #include <generic_delay_timer.h> 15 #ifdef SPD_opteed 16 #include <optee_utils.h> 17 #endif 18 #include <plat_arm.h> 19 #include <platform.h> 20 #include <platform_def.h> 21 #include <string.h> 22 #include <utils.h> 23 24 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 25 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 26 27 /* 28 * Check that BL2_BASE is atleast a page over ARM_BL_RAM_BASE. The page is for 29 * `meminfo_t` data structure and TB_FW_CONFIG passed from BL1. Not needed 30 * when BL2 is compiled for BL_AT_EL3 as BL2 doesn't need any info from BL1 and 31 * BL2 is loaded at base of usable SRAM. 32 */ 33 #if BL2_AT_EL3 34 #define BL1_MEMINFO_OFFSET 0x0 35 #else 36 #define BL1_MEMINFO_OFFSET PAGE_SIZE 37 #endif 38 39 CASSERT(BL2_BASE >= (ARM_BL_RAM_BASE + BL1_MEMINFO_OFFSET), assert_bl2_base_overflows); 40 41 /* Weak definitions may be overridden in specific ARM standard platform */ 42 #pragma weak bl2_early_platform_setup2 43 #pragma weak bl2_platform_setup 44 #pragma weak bl2_plat_arch_setup 45 #pragma weak bl2_plat_sec_mem_layout 46 47 #if LOAD_IMAGE_V2 48 49 #pragma weak bl2_plat_handle_post_image_load 50 51 #else /* LOAD_IMAGE_V2 */ 52 53 /******************************************************************************* 54 * This structure represents the superset of information that is passed to 55 * BL31, e.g. while passing control to it from BL2, bl31_params 56 * and other platform specific params 57 ******************************************************************************/ 58 typedef struct bl2_to_bl31_params_mem { 59 bl31_params_t bl31_params; 60 image_info_t bl31_image_info; 61 image_info_t bl32_image_info; 62 image_info_t bl33_image_info; 63 entry_point_info_t bl33_ep_info; 64 entry_point_info_t bl32_ep_info; 65 entry_point_info_t bl31_ep_info; 66 } bl2_to_bl31_params_mem_t; 67 68 69 static bl2_to_bl31_params_mem_t bl31_params_mem; 70 71 72 /* Weak definitions may be overridden in specific ARM standard platform */ 73 #pragma weak bl2_plat_get_bl31_params 74 #pragma weak bl2_plat_get_bl31_ep_info 75 #pragma weak bl2_plat_flush_bl31_params 76 #pragma weak bl2_plat_set_bl31_ep_info 77 #pragma weak bl2_plat_get_scp_bl2_meminfo 78 #pragma weak bl2_plat_get_bl32_meminfo 79 #pragma weak bl2_plat_set_bl32_ep_info 80 #pragma weak bl2_plat_get_bl33_meminfo 81 #pragma weak bl2_plat_set_bl33_ep_info 82 83 #if ARM_BL31_IN_DRAM 84 meminfo_t *bl2_plat_sec_mem_layout(void) 85 { 86 static meminfo_t bl2_dram_layout 87 __aligned(CACHE_WRITEBACK_GRANULE) = { 88 .total_base = BL31_BASE, 89 .total_size = (ARM_AP_TZC_DRAM1_BASE + 90 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE, 91 .free_base = BL31_BASE, 92 .free_size = (ARM_AP_TZC_DRAM1_BASE + 93 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE 94 }; 95 96 return &bl2_dram_layout; 97 } 98 #else 99 meminfo_t *bl2_plat_sec_mem_layout(void) 100 { 101 return &bl2_tzram_layout; 102 } 103 #endif /* ARM_BL31_IN_DRAM */ 104 105 /******************************************************************************* 106 * This function assigns a pointer to the memory that the platform has kept 107 * aside to pass platform specific and trusted firmware related information 108 * to BL31. This memory is allocated by allocating memory to 109 * bl2_to_bl31_params_mem_t structure which is a superset of all the 110 * structure whose information is passed to BL31 111 * NOTE: This function should be called only once and should be done 112 * before generating params to BL31 113 ******************************************************************************/ 114 bl31_params_t *bl2_plat_get_bl31_params(void) 115 { 116 bl31_params_t *bl2_to_bl31_params; 117 118 /* 119 * Initialise the memory for all the arguments that needs to 120 * be passed to BL31 121 */ 122 zeromem(&bl31_params_mem, sizeof(bl2_to_bl31_params_mem_t)); 123 124 /* Assign memory for TF related information */ 125 bl2_to_bl31_params = &bl31_params_mem.bl31_params; 126 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); 127 128 /* Fill BL31 related information */ 129 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info; 130 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY, 131 VERSION_1, 0); 132 133 /* Fill BL32 related information if it exists */ 134 #ifdef BL32_BASE 135 bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; 136 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP, 137 VERSION_1, 0); 138 bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; 139 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY, 140 VERSION_1, 0); 141 #endif /* BL32_BASE */ 142 143 /* Fill BL33 related information */ 144 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; 145 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, 146 PARAM_EP, VERSION_1, 0); 147 148 /* BL33 expects to receive the primary CPU MPID (through x0) */ 149 bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); 150 151 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; 152 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY, 153 VERSION_1, 0); 154 155 return bl2_to_bl31_params; 156 } 157 158 /* Flush the TF params and the TF plat params */ 159 void bl2_plat_flush_bl31_params(void) 160 { 161 flush_dcache_range((unsigned long)&bl31_params_mem, 162 sizeof(bl2_to_bl31_params_mem_t)); 163 } 164 165 /******************************************************************************* 166 * This function returns a pointer to the shared memory that the platform 167 * has kept to point to entry point information of BL31 to BL2 168 ******************************************************************************/ 169 struct entry_point_info *bl2_plat_get_bl31_ep_info(void) 170 { 171 #if DEBUG 172 bl31_params_mem.bl31_ep_info.args.arg3 = ARM_BL31_PLAT_PARAM_VAL; 173 #endif 174 175 return &bl31_params_mem.bl31_ep_info; 176 } 177 #endif /* LOAD_IMAGE_V2 */ 178 179 /******************************************************************************* 180 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 181 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 182 * Copy it to a safe location before its reclaimed by later BL2 functionality. 183 ******************************************************************************/ 184 void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, meminfo_t *mem_layout) 185 { 186 /* Initialize the console to provide early debug support */ 187 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 188 ARM_CONSOLE_BAUDRATE); 189 190 /* Setup the BL2 memory layout */ 191 bl2_tzram_layout = *mem_layout; 192 193 /* Initialise the IO layer and register platform IO devices */ 194 plat_arm_io_setup(); 195 196 #if LOAD_IMAGE_V2 197 if (tb_fw_config != 0U) 198 arm_bl2_set_tb_cfg_addr((void *)tb_fw_config); 199 #endif 200 } 201 202 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 203 { 204 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 205 206 generic_delay_timer_init(); 207 } 208 209 /* 210 * Perform BL2 preload setup. Currently we initialise the dynamic 211 * configuration here. 212 */ 213 void bl2_plat_preload_setup(void) 214 { 215 #if LOAD_IMAGE_V2 216 arm_bl2_dyn_cfg_init(); 217 #endif 218 } 219 220 /* 221 * Perform ARM standard platform setup. 222 */ 223 void arm_bl2_platform_setup(void) 224 { 225 /* Initialize the secure environment */ 226 plat_arm_security_setup(); 227 228 #if defined(PLAT_ARM_MEM_PROT_ADDR) 229 arm_nor_psci_do_static_mem_protect(); 230 #endif 231 } 232 233 void bl2_platform_setup(void) 234 { 235 arm_bl2_platform_setup(); 236 } 237 238 /******************************************************************************* 239 * Perform the very early platform specific architectural setup here. At the 240 * moment this is only initializes the mmu in a quick and dirty way. 241 ******************************************************************************/ 242 void arm_bl2_plat_arch_setup(void) 243 { 244 arm_setup_page_tables(bl2_tzram_layout.total_base, 245 bl2_tzram_layout.total_size, 246 BL_CODE_BASE, 247 BL_CODE_END, 248 BL_RO_DATA_BASE, 249 BL_RO_DATA_END 250 #if USE_COHERENT_MEM 251 , BL_COHERENT_RAM_BASE, 252 BL_COHERENT_RAM_END 253 #endif 254 ); 255 256 #ifdef AARCH32 257 enable_mmu_secure(0); 258 #else 259 enable_mmu_el1(0); 260 #endif 261 } 262 263 void bl2_plat_arch_setup(void) 264 { 265 arm_bl2_plat_arch_setup(); 266 } 267 268 #if LOAD_IMAGE_V2 269 int arm_bl2_handle_post_image_load(unsigned int image_id) 270 { 271 int err = 0; 272 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 273 #ifdef SPD_opteed 274 bl_mem_params_node_t *pager_mem_params = NULL; 275 bl_mem_params_node_t *paged_mem_params = NULL; 276 #endif 277 assert(bl_mem_params); 278 279 switch (image_id) { 280 #ifdef AARCH64 281 case BL32_IMAGE_ID: 282 #ifdef SPD_opteed 283 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 284 assert(pager_mem_params); 285 286 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 287 assert(paged_mem_params); 288 289 err = parse_optee_header(&bl_mem_params->ep_info, 290 &pager_mem_params->image_info, 291 &paged_mem_params->image_info); 292 if (err != 0) { 293 WARN("OPTEE header parse error.\n"); 294 } 295 #endif 296 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 297 break; 298 #endif 299 300 case BL33_IMAGE_ID: 301 /* BL33 expects to receive the primary CPU MPID (through r0) */ 302 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 303 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 304 break; 305 306 #ifdef SCP_BL2_BASE 307 case SCP_BL2_IMAGE_ID: 308 /* The subsequent handling of SCP_BL2 is platform specific */ 309 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 310 if (err) { 311 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 312 } 313 break; 314 #endif 315 default: 316 /* Do nothing in default case */ 317 break; 318 } 319 320 return err; 321 } 322 323 /******************************************************************************* 324 * This function can be used by the platforms to update/use image 325 * information for given `image_id`. 326 ******************************************************************************/ 327 int bl2_plat_handle_post_image_load(unsigned int image_id) 328 { 329 return arm_bl2_handle_post_image_load(image_id); 330 } 331 332 #else /* LOAD_IMAGE_V2 */ 333 334 /******************************************************************************* 335 * Populate the extents of memory available for loading SCP_BL2 (if used), 336 * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2. 337 ******************************************************************************/ 338 void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo) 339 { 340 *scp_bl2_meminfo = bl2_tzram_layout; 341 } 342 343 /******************************************************************************* 344 * Before calling this function BL31 is loaded in memory and its entrypoint 345 * is set by load_image. This is a placeholder for the platform to change 346 * the entrypoint of BL31 and set SPSR and security state. 347 * On ARM standard platforms we only set the security state of the entrypoint 348 ******************************************************************************/ 349 void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info, 350 entry_point_info_t *bl31_ep_info) 351 { 352 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); 353 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, 354 DISABLE_ALL_EXCEPTIONS); 355 } 356 357 358 /******************************************************************************* 359 * Before calling this function BL32 is loaded in memory and its entrypoint 360 * is set by load_image. This is a placeholder for the platform to change 361 * the entrypoint of BL32 and set SPSR and security state. 362 * On ARM standard platforms we only set the security state of the entrypoint 363 ******************************************************************************/ 364 #ifdef BL32_BASE 365 void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, 366 entry_point_info_t *bl32_ep_info) 367 { 368 SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); 369 bl32_ep_info->spsr = arm_get_spsr_for_bl32_entry(); 370 } 371 372 /******************************************************************************* 373 * Populate the extents of memory available for loading BL32 374 ******************************************************************************/ 375 void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) 376 { 377 /* 378 * Populate the extents of memory available for loading BL32. 379 */ 380 bl32_meminfo->total_base = BL32_BASE; 381 bl32_meminfo->free_base = BL32_BASE; 382 bl32_meminfo->total_size = 383 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 384 bl32_meminfo->free_size = 385 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 386 } 387 #endif /* BL32_BASE */ 388 389 /******************************************************************************* 390 * Before calling this function BL33 is loaded in memory and its entrypoint 391 * is set by load_image. This is a placeholder for the platform to change 392 * the entrypoint of BL33 and set SPSR and security state. 393 * On ARM standard platforms we only set the security state of the entrypoint 394 ******************************************************************************/ 395 void bl2_plat_set_bl33_ep_info(image_info_t *image, 396 entry_point_info_t *bl33_ep_info) 397 { 398 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); 399 bl33_ep_info->spsr = arm_get_spsr_for_bl33_entry(); 400 } 401 402 /******************************************************************************* 403 * Populate the extents of memory available for loading BL33 404 ******************************************************************************/ 405 void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) 406 { 407 bl33_meminfo->total_base = ARM_NS_DRAM1_BASE; 408 bl33_meminfo->total_size = ARM_NS_DRAM1_SIZE; 409 bl33_meminfo->free_base = ARM_NS_DRAM1_BASE; 410 bl33_meminfo->free_size = ARM_NS_DRAM1_SIZE; 411 } 412 413 #endif /* LOAD_IMAGE_V2 */ 414