1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <arm_def.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <debug.h> 12 #include <desc_image_load.h> 13 #include <generic_delay_timer.h> 14 #ifdef SPD_opteed 15 #include <optee_utils.h> 16 #endif 17 #include <plat_arm.h> 18 #include <platform.h> 19 #include <platform_def.h> 20 #include <string.h> 21 #include <utils.h> 22 23 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 24 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 25 26 /* 27 * Check that BL2_BASE is above ARM_TB_FW_CONFIG_LIMIT. This reserved page is 28 * for `meminfo_t` data structure and fw_configs passed from BL1. 29 */ 30 CASSERT(BL2_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl2_base_overflows); 31 32 /* Weak definitions may be overridden in specific ARM standard platform */ 33 #pragma weak bl2_early_platform_setup2 34 #pragma weak bl2_platform_setup 35 #pragma weak bl2_plat_arch_setup 36 #pragma weak bl2_plat_sec_mem_layout 37 38 #if LOAD_IMAGE_V2 39 40 #pragma weak bl2_plat_handle_post_image_load 41 42 #else /* LOAD_IMAGE_V2 */ 43 44 /******************************************************************************* 45 * This structure represents the superset of information that is passed to 46 * BL31, e.g. while passing control to it from BL2, bl31_params 47 * and other platform specific params 48 ******************************************************************************/ 49 typedef struct bl2_to_bl31_params_mem { 50 bl31_params_t bl31_params; 51 image_info_t bl31_image_info; 52 image_info_t bl32_image_info; 53 image_info_t bl33_image_info; 54 entry_point_info_t bl33_ep_info; 55 entry_point_info_t bl32_ep_info; 56 entry_point_info_t bl31_ep_info; 57 } bl2_to_bl31_params_mem_t; 58 59 60 static bl2_to_bl31_params_mem_t bl31_params_mem; 61 62 63 /* Weak definitions may be overridden in specific ARM standard platform */ 64 #pragma weak bl2_plat_get_bl31_params 65 #pragma weak bl2_plat_get_bl31_ep_info 66 #pragma weak bl2_plat_flush_bl31_params 67 #pragma weak bl2_plat_set_bl31_ep_info 68 #pragma weak bl2_plat_get_scp_bl2_meminfo 69 #pragma weak bl2_plat_get_bl32_meminfo 70 #pragma weak bl2_plat_set_bl32_ep_info 71 #pragma weak bl2_plat_get_bl33_meminfo 72 #pragma weak bl2_plat_set_bl33_ep_info 73 74 #if ARM_BL31_IN_DRAM 75 meminfo_t *bl2_plat_sec_mem_layout(void) 76 { 77 static meminfo_t bl2_dram_layout 78 __aligned(CACHE_WRITEBACK_GRANULE) = { 79 .total_base = BL31_BASE, 80 .total_size = (ARM_AP_TZC_DRAM1_BASE + 81 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE, 82 .free_base = BL31_BASE, 83 .free_size = (ARM_AP_TZC_DRAM1_BASE + 84 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE 85 }; 86 87 return &bl2_dram_layout; 88 } 89 #else 90 meminfo_t *bl2_plat_sec_mem_layout(void) 91 { 92 return &bl2_tzram_layout; 93 } 94 #endif /* ARM_BL31_IN_DRAM */ 95 96 /******************************************************************************* 97 * This function assigns a pointer to the memory that the platform has kept 98 * aside to pass platform specific and trusted firmware related information 99 * to BL31. This memory is allocated by allocating memory to 100 * bl2_to_bl31_params_mem_t structure which is a superset of all the 101 * structure whose information is passed to BL31 102 * NOTE: This function should be called only once and should be done 103 * before generating params to BL31 104 ******************************************************************************/ 105 bl31_params_t *bl2_plat_get_bl31_params(void) 106 { 107 bl31_params_t *bl2_to_bl31_params; 108 109 /* 110 * Initialise the memory for all the arguments that needs to 111 * be passed to BL31 112 */ 113 zeromem(&bl31_params_mem, sizeof(bl2_to_bl31_params_mem_t)); 114 115 /* Assign memory for TF related information */ 116 bl2_to_bl31_params = &bl31_params_mem.bl31_params; 117 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); 118 119 /* Fill BL31 related information */ 120 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info; 121 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY, 122 VERSION_1, 0); 123 124 /* Fill BL32 related information if it exists */ 125 #ifdef BL32_BASE 126 bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; 127 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP, 128 VERSION_1, 0); 129 bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; 130 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY, 131 VERSION_1, 0); 132 #endif /* BL32_BASE */ 133 134 /* Fill BL33 related information */ 135 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; 136 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, 137 PARAM_EP, VERSION_1, 0); 138 139 /* BL33 expects to receive the primary CPU MPID (through x0) */ 140 bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); 141 142 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; 143 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY, 144 VERSION_1, 0); 145 146 return bl2_to_bl31_params; 147 } 148 149 /* Flush the TF params and the TF plat params */ 150 void bl2_plat_flush_bl31_params(void) 151 { 152 flush_dcache_range((unsigned long)&bl31_params_mem, 153 sizeof(bl2_to_bl31_params_mem_t)); 154 } 155 156 /******************************************************************************* 157 * This function returns a pointer to the shared memory that the platform 158 * has kept to point to entry point information of BL31 to BL2 159 ******************************************************************************/ 160 struct entry_point_info *bl2_plat_get_bl31_ep_info(void) 161 { 162 #if DEBUG 163 bl31_params_mem.bl31_ep_info.args.arg3 = ARM_BL31_PLAT_PARAM_VAL; 164 #endif 165 166 return &bl31_params_mem.bl31_ep_info; 167 } 168 #endif /* LOAD_IMAGE_V2 */ 169 170 /******************************************************************************* 171 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 172 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 173 * Copy it to a safe location before its reclaimed by later BL2 functionality. 174 ******************************************************************************/ 175 void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, 176 struct meminfo *mem_layout) 177 { 178 /* Initialize the console to provide early debug support */ 179 arm_console_boot_init(); 180 181 /* Setup the BL2 memory layout */ 182 bl2_tzram_layout = *mem_layout; 183 184 /* Initialise the IO layer and register platform IO devices */ 185 plat_arm_io_setup(); 186 187 #if LOAD_IMAGE_V2 188 if (tb_fw_config != 0U) 189 arm_bl2_set_tb_cfg_addr((void *)tb_fw_config); 190 #endif 191 } 192 193 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 194 { 195 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 196 197 generic_delay_timer_init(); 198 } 199 200 /* 201 * Perform BL2 preload setup. Currently we initialise the dynamic 202 * configuration here. 203 */ 204 void bl2_plat_preload_setup(void) 205 { 206 #if LOAD_IMAGE_V2 207 arm_bl2_dyn_cfg_init(); 208 #endif 209 } 210 211 /* 212 * Perform ARM standard platform setup. 213 */ 214 void arm_bl2_platform_setup(void) 215 { 216 /* Initialize the secure environment */ 217 plat_arm_security_setup(); 218 219 #if defined(PLAT_ARM_MEM_PROT_ADDR) 220 arm_nor_psci_do_static_mem_protect(); 221 #endif 222 } 223 224 void bl2_platform_setup(void) 225 { 226 arm_bl2_platform_setup(); 227 } 228 229 /******************************************************************************* 230 * Perform the very early platform specific architectural setup here. At the 231 * moment this is only initializes the mmu in a quick and dirty way. 232 ******************************************************************************/ 233 void arm_bl2_plat_arch_setup(void) 234 { 235 arm_setup_page_tables(bl2_tzram_layout.total_base, 236 bl2_tzram_layout.total_size, 237 BL_CODE_BASE, 238 BL_CODE_END, 239 BL_RO_DATA_BASE, 240 BL_RO_DATA_END 241 #if USE_COHERENT_MEM 242 , BL_COHERENT_RAM_BASE, 243 BL_COHERENT_RAM_END 244 #endif 245 ); 246 247 #ifdef AARCH32 248 enable_mmu_secure(0); 249 #else 250 enable_mmu_el1(0); 251 #endif 252 } 253 254 void bl2_plat_arch_setup(void) 255 { 256 arm_bl2_plat_arch_setup(); 257 } 258 259 #if LOAD_IMAGE_V2 260 int arm_bl2_handle_post_image_load(unsigned int image_id) 261 { 262 int err = 0; 263 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 264 #ifdef SPD_opteed 265 bl_mem_params_node_t *pager_mem_params = NULL; 266 bl_mem_params_node_t *paged_mem_params = NULL; 267 #endif 268 assert(bl_mem_params); 269 270 switch (image_id) { 271 #ifdef AARCH64 272 case BL32_IMAGE_ID: 273 #ifdef SPD_opteed 274 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 275 assert(pager_mem_params); 276 277 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 278 assert(paged_mem_params); 279 280 err = parse_optee_header(&bl_mem_params->ep_info, 281 &pager_mem_params->image_info, 282 &paged_mem_params->image_info); 283 if (err != 0) { 284 WARN("OPTEE header parse error.\n"); 285 } 286 #endif 287 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 288 break; 289 #endif 290 291 case BL33_IMAGE_ID: 292 /* BL33 expects to receive the primary CPU MPID (through r0) */ 293 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 294 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 295 break; 296 297 #ifdef SCP_BL2_BASE 298 case SCP_BL2_IMAGE_ID: 299 /* The subsequent handling of SCP_BL2 is platform specific */ 300 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 301 if (err) { 302 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 303 } 304 break; 305 #endif 306 default: 307 /* Do nothing in default case */ 308 break; 309 } 310 311 return err; 312 } 313 314 /******************************************************************************* 315 * This function can be used by the platforms to update/use image 316 * information for given `image_id`. 317 ******************************************************************************/ 318 int bl2_plat_handle_post_image_load(unsigned int image_id) 319 { 320 return arm_bl2_handle_post_image_load(image_id); 321 } 322 323 #else /* LOAD_IMAGE_V2 */ 324 325 /******************************************************************************* 326 * Populate the extents of memory available for loading SCP_BL2 (if used), 327 * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2. 328 ******************************************************************************/ 329 void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo) 330 { 331 *scp_bl2_meminfo = bl2_tzram_layout; 332 } 333 334 /******************************************************************************* 335 * Before calling this function BL31 is loaded in memory and its entrypoint 336 * is set by load_image. This is a placeholder for the platform to change 337 * the entrypoint of BL31 and set SPSR and security state. 338 * On ARM standard platforms we only set the security state of the entrypoint 339 ******************************************************************************/ 340 void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info, 341 entry_point_info_t *bl31_ep_info) 342 { 343 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); 344 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, 345 DISABLE_ALL_EXCEPTIONS); 346 } 347 348 349 /******************************************************************************* 350 * Before calling this function BL32 is loaded in memory and its entrypoint 351 * is set by load_image. This is a placeholder for the platform to change 352 * the entrypoint of BL32 and set SPSR and security state. 353 * On ARM standard platforms we only set the security state of the entrypoint 354 ******************************************************************************/ 355 #ifdef BL32_BASE 356 void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, 357 entry_point_info_t *bl32_ep_info) 358 { 359 SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); 360 bl32_ep_info->spsr = arm_get_spsr_for_bl32_entry(); 361 } 362 363 /******************************************************************************* 364 * Populate the extents of memory available for loading BL32 365 ******************************************************************************/ 366 void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) 367 { 368 /* 369 * Populate the extents of memory available for loading BL32. 370 */ 371 bl32_meminfo->total_base = BL32_BASE; 372 bl32_meminfo->free_base = BL32_BASE; 373 bl32_meminfo->total_size = 374 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 375 bl32_meminfo->free_size = 376 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 377 } 378 #endif /* BL32_BASE */ 379 380 /******************************************************************************* 381 * Before calling this function BL33 is loaded in memory and its entrypoint 382 * is set by load_image. This is a placeholder for the platform to change 383 * the entrypoint of BL33 and set SPSR and security state. 384 * On ARM standard platforms we only set the security state of the entrypoint 385 ******************************************************************************/ 386 void bl2_plat_set_bl33_ep_info(image_info_t *image, 387 entry_point_info_t *bl33_ep_info) 388 { 389 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); 390 bl33_ep_info->spsr = arm_get_spsr_for_bl33_entry(); 391 } 392 393 /******************************************************************************* 394 * Populate the extents of memory available for loading BL33 395 ******************************************************************************/ 396 void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) 397 { 398 bl33_meminfo->total_base = ARM_NS_DRAM1_BASE; 399 bl33_meminfo->total_size = ARM_NS_DRAM1_SIZE; 400 bl33_meminfo->free_base = ARM_NS_DRAM1_BASE; 401 bl33_meminfo->free_size = ARM_NS_DRAM1_SIZE; 402 } 403 404 #endif /* LOAD_IMAGE_V2 */ 405